CH7004C Datasheet, PDF (35/51 Pages) List of Unclassifed Manufacturers – Digital PC to TV Encoder with Macrovision

CHRONTEL
Register Descriptions (continued)
Input Data Format Register
Bit:
7
Symbol:
Type:
Default:
6
DACG
R/W
0
5
4
RGBBP
R/W
0
3
IDF3
R/W
0
2
IDF2
R/W
0
This register sets the variables required to define the incoming pixel data stream.
CH7004C
Symbol: IDF
Address: 04H
Bits: 7
1
IDF1
R/W
0
0
IDF0
R/W
0
Table 21. Input Data Format
IDF[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001-1111
Description
16-bit non-multiplexed RGB (16-bit color, 565) input
16-bit non-multiplexed YCrCb (24-bit color) input (Y non-multiplexed, CrCb multiplexed
16-bit multiplexed RGB (24-bit color) input
15-bit non-multiplexed RGB (15-bit color, 555) input
12-bit multiplexed RGB (24-bit color) input (“C” multiplex scheme)
12-bit multiplexed RGB2 (24-bit color) input (“I” multiplex scheme)
8-bit multiplexed RGB (24-bit color, 888) input
8-bit multiplexed RGB (16-bit color, 565) input
8-bit multiplexed RGB (15-bit color, 555) input
8-bit multiplexed YCrCb (24-bit color) input (Y, Cr and Cb are multiplexed)
RGBBP (bit 5): Setting this bit enables the RGB pass-through mode. Setting this bit to a 1 causes the input RGB
signal to be directly output at the DACs (subject to a pipeline delay). If RGBBP=0, the bypass mode is disabled.
DACG (bit 6): This bit controls the gain of the D/A converters. When DACG=0, the nominal DAC current is 71
µA, which provides the correct levels for NTSC and PAL-M. When DACG=1, the nominal DAC current is 76µA,
which provides the correct levels for PAL and NTSC-J.
Clock Mode Register
Bit:
Symbol:
Type:
Default:
7
CFRB
R/W
0
6
M/S*
R/W
0
5
Reserved
R/W
0
4
MCP
R/W
1
3
XCM1
R/W
0
2
XCM0
R/W
0
Symbol: CM
Address: 06H
Bits: 8
1
PCM1
R/W
0
0
PCM0
R/W
0
The setting of the clock mode bits determines the clocking mechanism used in the CH7004. The clock modes are
shown in the table below. PCM controls the frequency of the pixel clock, and XCM identifies the frequency of the
XCLK input clock.
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