CP80S54 Datasheet, PDF (35/47 Pages) List of Unclassifed Manufacturers – EPROM/ROM-Based 8-Bit Microcontroller Series

CP80S54/56
SLEEP
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
SBCAR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
SUBAR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
SUBIA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
SWAPR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Enter SLEEP Mode
SLEEP
None
00h Æ WDT;
00h Æ WDT prescaler;
1 Æ TO ;
0 Æ PD
TO _, PD
Time-out status bit ( TO ) is set. The power-down status bit ( PD ) is cleared. The WDT and its
prescaler are cleared.
The processor is put into SLEEP mode.
1
Subtract ACC from R with Carry
SBCAR R, d
0 ≤ R ≤ 63
d∈ [0,1]
R + ACC + C Æ dest
C, DC, Z
Add the 2’s complement data of the ACC register from register ‘R’ with Carry. If ‘d’ is 0 the
result is stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Subtract ACC from R
SUBAR R, d
0 ≤ R ≤ 63
d∈ [0,1]
R - ACC Æ dest
C, DC, Z
Subtract (2’s complement method) the ACC register from register ‘R’. If ‘d’ is 0 the result is
stored in the ACC register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Subtract ACC from Immediate
SUBIA I
0 ≤ I ≤ 255
I - ACC Æ ACC
C, DC, Z
Subtract (2’s complement method) the ACC register from the 8-bit immediate ‘I’. The result is
placed in the ACC register.
1
Swap nibbles in R
SWAPR R, d
0 ≤ R ≤ 63
d∈ [0,1]
R<3:0> Æ dest<7:4>;
R<7:4> Æ dest<3:0>
None
The upper and lower nibbles of register ‘R’ are exchanged. If ‘d’ is 0 the result is placed in
ACC register. If ‘d’ is 1 the result in placed in register ‘R’.
1
Rev0.1 Nov 30, 2005
P.35/CP80S54/S56