CP80S54 Datasheet, PDF (14/47 Pages) List of Unclassifed Manufacturers – EPROM/ROM-Based 8-Bit Microcontroller Series

CP80S54/56
2.1.16 OPTION Register
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
N/A (w) OPTION
-
INTEDG T0CS T0SE PSA
PS2
PS1
PS0
Accessed by OPTION instruction.
By executing the OPTION instruction, the contents of the ACC Register will be transferred to the OPTION Register.
The OPTION Register is a 7-bit wide, write-only register which contains various control bits to configure the
Timer0/WDT prescaler, Timer0, and the external INT interrupt.
The OPTION Register are “write-only” and are set all “1”s except INTEDG bit.
PS2:PS0 : Prescaler rate select bits.
PS2:PS0
000
001
010
011
100
101
110
111
Timer0 Rate
1:2
1:4
1:8
1:16
1:32
1:64
1:128
1:256
WDT Rate
1:1
1:2
1:4
1:8
1:16
1:32
1:64
1:128
PSA : Prescaler assign bit.
= 1, WDT (watch-dog timer).
= 0, TMR0 (Timer0).
T0SE : TMR0 source edge select bit.
= 1, Falling edge on T0CKI pin.
= 0, Rising edge on T0CKI pin.
T0CS : TMR0 clock source select bit.
= 1, External T0CKI pin.
= 0, internal instruction clock cycle.
INTEDG : Interrupt edge select bit.
= 1, interrupt on rising edge of INT pin.
= 0, interrupt on falling edge of INT pin.
Bit7 : Not used.
2.1.17 IOSTA, & IOSTB (Port I/O Control Registers)
Address
Name
B7
B6
B5
B4
B3
B2
B1
B0
N/A (w)
N/A (w)
IOSTA
IOSTB
Port A I/O Control Register
Port B I/O Control Register
Accessed by IOST instruction.
The Port I/O Control Registers are loaded with the contents of the ACC Register by executing the IOST R (05h~06h)
instruction. A ‘1’ from a IOST Register bit puts the corresponding output driver in hi-impedance state (input mode).
A ‘0’ enables the output buffer and puts the contents of the output data latch on the selected pins (output mode).
The IOST Registers are “write-only” and are set (output drivers disabled) upon RESET.
Rev0.1 Nov 30, 2005
P.14/CP80S54/S56