CP80S54 Datasheet, PDF (30/47 Pages) List of Unclassifed Manufacturers – EPROM/ROM-Based 8-Bit Microcontroller Series

CP80S54/56
CLRA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
CLRR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
CLRWDT
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
COMR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
DAA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Clear ACC
CLRA
None
00h Æ ACC;
1ÆZ
Z
The ACC register is cleared. Zero bit (Z) is set.
1
Clear R
CLRR R
0 ≤ R ≤ 63
00h Æ R;
1ÆZ
Z
The contents of register ‘R’ are cleared and the Z bit is set.
1
Clear Watchdog Timer
CLRWDT
None
00h Æ WDT;
00h Æ WDT prescaler (if assigned);
1 Æ TO ;
1 Æ PD
TO _, PD
The CLRWDT instruction resets the WDT. It also resets the prescaler, if the prescaler is
assigned to the WDT and not Timer0. Status bits TO and PD are set.
1
Complement R
COMR R, d
0 ≤ R ≤ 63
d∈ [0,1]
R Æ dest
Z
The contents of register ‘R’ are complemented. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is 1 the result is stored back in register ‘R’.
1
Adjust ACC’s data format from HEX to DEC
DAA
None
ACC(hex) Æ ACC(dec)
C
Convert the ACC data from hexadecimal to decimal format after any addition
operation and restored to ACC.
1
Rev0.1 Nov 30, 2005
P.30/CP80S54/S56