CP80S54 Datasheet, PDF (28/47 Pages) List of Unclassifed Manufacturers – EPROM/ROM-Based 8-Bit Microcontroller Series

CP80S54/56
ADCAR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
ADDAR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
ADDIA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
ANDAR
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
ANDIA
Syntax:
Operands:
Operation:
Status Affected:
Description:
Cycles:
Add ACC and R with Carry
ADCAR R, d
0 ≤ R ≤ 63
d∈ [0,1]
R + ACC + C Æ dest
C, DC, Z
Add the contents of the ACC register and register ‘R’ with Carry. If ‘d’ is 0 the result is stored
in the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Add ACC and R
ADDAR R, d
0 ≤ R ≤ 63
d∈ [0,1]
ACC + R Æ dest
C, DC, Z
Add the contents of the ACC register and register ‘R’. If ‘d’ is 0 the result is stored in the ACC
register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
Add ACC and Immediate
ADDIA I
0 ≤ I ≤ 255
ACC + I Æ ACC
C, DC, Z
Add the contents of the ACC register with the 8-bit immediate ‘I’. The result is placed in the
ACC register.
1
AND ACC and R
ANDAR R, d
0 ≤ R ≤ 63
d∈ [0,1]
ACC and R Æ dest
Z
The contents of the ACC register are AND’ed with register ‘R’. If ‘d’ is 0 the result is stored in
the ACC register. If ‘d’ is ‘1’ the result is stored back in register ‘R’.
1
AND Immediate with ACC
ANDIA I
0 ≤ I ≤ 255
ACC AND I Æ ACC
Z
The contents of the ACC register are AND’ed with the 8-bit immediate ‘I’. The result is placed
in the ACC register.
1
Rev0.1 Nov 30, 2005
P.28/CP80S54/S56