EPC1064V Datasheet, PDF (33/36 Pages) List of Unclassifed Manufacturers – Configuration Devices for SRAM-Based LUT Devices

Configuration Devices for SRAM-Based LUT Devices Data Sheet
Table 22. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 &
EPC1441 Devices at 5.0-V
Symbol
Parameter
t_CE
t_OEZX
t_CO
t_MCH
t_MCL
f_CK
t_SCH
t_SCL
t_CASC
t_CCA
f_CDOE
t_OEC
t_NRCAS
t_NRR
OE high to first clock delay
OE high to data output enabled
DCLK to data out delay
DCLK high time for the first device in the
configuration chain
DCLK low time for the first device in the
configuration chain
Clock frequency
DCLK high time for subsequent devices
DCLK low time for subsequent devices
CLK rising edge to nCASC
nCS to nCASC cascade delay
CLK to data enable/disable
OE low to CLK disable delay
OE low (reset) to nCASC delay
OE low time (reset) minimum
Conditions
Min
Typ
Max
200
50
20
30
50
75
30
50
75
6.7
10
16.7
30
30
20
10
20
20
25
100
Unit
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Table 23. ACEX 1K, FLEX 10K & FLEX 6000 Device Configuration Parameters Using EPC1 &
EPC1441 Devices at 3.3-V
Symbol
Parameter
t_CE
t_OEZX
t_CO
t_MCH
t_MCL
f_CK
t_SCH
t_SCL
t_CASC
t_CCA
f_CDOE
t_OEC
t_NRCAS
t_NRR
OE high to first clock delay
OE high to data output enabled
DCLK to data out delay
DCLK high time for the first device in the
configuration chain
DCLK low time for the first device in the
configuration chain
Clock frequency
DCLK high time for subsequent devices
DCLK low time for subsequent devices
CLK rising edge to nCASC
nCS to nCASC cascade delay
CLK to data enable/disable
OE low to CLK disable delay
OE low (reset) to nCASC delay
OE low time (reset) minimum
Conditions
Min
Typ
Max
300
80
30
50
125
250
50
125
250
2
4
10
50
50
25
15
30
30
30
100
Unit
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Altera Corporation
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