EPC1064V Datasheet, PDF (10/36 Pages) List of Unclassifed Manufacturers – Configuration Devices for SRAM-Based LUT Devices

Configuration Devices for SRAM-based LUT Devices Data Sheet
Table 3 describes EPC2, EPC1, and EPC1441 pin functions during
APEX II, APEX 20K, Mercury, ACEX 1K, and FLEX device configuration.
For information on EPC4, EPC8, and EPC16 devices, refer to Enhanced
Configuration Devices (EPC4, EPC8, & EPC16) Data Sheet.
Table 3. EPC2, EPC1, & EPC1441 Pin Functions During APEX II, APEX 20K, Mercury, ACEX 1K, FLEX 10K
& FLEX 6000 Configuration (Part 1 of 3) Notes (1), (2)
Pin Name
DATA
DCLK
OE (5)
nCS (5)
Pin Number
Pin
8-Pin 20-Pin 32-Pin ^Type
PDIP (3) PLCC TQFP (4)
1
2
31
Output
2
4
2
I/O
3
8
7
Open-
Drain
I/O
4
9
10
Input
Description
Serial data output. The DATA pin is tri-stated before
configuration when the nCS pin is high, and after the
configuration device finishes sending its configuration
data. This operation is independent of the device’s
position in the cascade chain.
DCLK is a clock output when configuring with a single
configuration device or when the configuration device is
the first device in a configuration device chain. DCLK is
a clock input for subsequent configuration devices in a
configuration device chain. Rising edges on DCLK
increment the internal address counter and present the
next bit of data to the DATA pin. The counter is
incremented only if the OE input is held high, the nCS
input is held low, and all configuration data has not
been transferred to the target device. When configuring
with the first EPC2 or EPC1 device in a configuration
device chain or with a single EPC1441 device, the
DCLK pin drives low after configuration is complete or
when OE is low.
Output enable (active high) and reset (active low). A
low logic level resets the address counter. A high logic
level enables DATA and permits the address counter to
count. If this pin is low (reset) during configuration, the
internal oscillator becomes inactive and DCLK drives
low. See “Error Detection Circuitry” on page 23.
Chip select input (active low). A low input allows DCLK
to increment the address counter and enables DATA to
drive out. If the EPC1 or EPC2 is reset with nCS low, the
device initializes as the first device in a configuration
chain. If the EPC1 or EPC2 device is reset with nCS
high, the device initializes as the subsequent device in
the chain.
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Altera Corporation