EPC1064V Datasheet, PDF (17/36 Pages) List of Unclassifed Manufacturers – Configuration Devices for SRAM-Based LUT Devices

Configuration Devices for SRAM-Based LUT Devices Data Sheet
Table 4 defines the APEX 20K, FLEX 10K, and FLEX 6000 timing
parameters when using EPC2 devices at 3.3 V.
Table 4. APEX 20K, FLEX 10K & FLEX 6000 Timing Parameters using EPC2
Devices at 3.3 V Note (1)
Symbol
Parameter
Min Max Units
t_POR
t_OEZX
t_CH
t_CL
t_DSU
t_DH
t_CO
t_OEW
f_CLK
POR delay (2)
200
ms
OE high to DATA output enabled
80
ns
DCLK high time
40
100
ns
DCLK low time
40
100
ns
Data setup time before rising edge on
30
ns
DCLK
Data hold time after rising edge on DCLK 0
ns
DCLK to DATA out
30
ns
OE low pulse width to guarantee counter 100
ns
reset
DCLK frequency
5
12.5 MHz
Notes to Table 4:
(1) For more information regarding EPC4, EPC8, or EPC16 configuration device timing
parameters, see the Enhanced Configuration Device (EPC4, EPC8 & EPC16) Data Sheet.
(2) The configuration device imposes a POR delay upon initial power-up to allow the
voltage supply to stabilize. Subsequent reconfigurations do not incur this delay.
Altera Corporation
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