ICM320T Datasheet, PDF (27/30 Pages) List of Unclassifed Manufacturers – 3.2 Megapixel QXGA Digital Color CMOS Image Sensor

ICM320T
3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor
Preliminary Data Sheet V1.0
1/16-Rate Subsampling Mode LineTiming
For the default 1/16-rate (512x384) line timing, a line starts when the HSYNC signal is de-asserted. The
HSYNC signal will be low for 16 PCLK clock cycles. After 25 PCLK clock cycles, DOUT [9:0] will
output three cycles of dummy pixel data, followed by 512 cycles of image data and another three dummy
pixel data. Seven clock cycles later, the HSYNC signal will be de-asserted to start a new line. See Figure
13.
Figure 13. Default 1/16-Rate Line Timing for 570 PCLKs
1/16-Rate Subsampling Mode Frame Timing
For the default 1/16-rate (512x384) frame timing, the timing unit for the frame is derived from one line-
time unit, which is 550 PCLKs. The frame timing starts when the VSYNC signal is de-asserted. The
VSYNC signal will be low for three line-time units. Four line-time units from the start of the frame, DOUT
[9:0] will output three lines of dummy pixel data followed by 384 lines of image data and another three
lines of dummy pixel data. Eleven (11) clock cycles later, the VSYNC signal will be de-asserted again to
start a new frame. See Figure 14.
Figure 14. Default 1/16-Rate Frame Timing - Change Registers 0x14/0x15 to 0x0010 (H)
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3/14/2005