ICM320T Datasheet, PDF (26/30 Pages) List of Unclassifed Manufacturers – 3.2 Megapixel QXGA Digital Color CMOS Image Sensor

ICM320T
3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor
Preliminary Data Sheet V1.0
1/4-Rate Subsampling Mode Line Timing
For the default 1/4-rate (1024x768) line timing, a line starts when the HSYNC signal is de-asserted. The
HSYNC signal will be low for 32 PCLK clock cycles. After 50 PCLK clock cycles, DOUT [9:0] will
output five cycles of dummy pixel data, followed by 1024 cycles of image data and another five cycles of
dummy pixel data. Sixteen cycles after the last dummy pixel data, the VSYNC signal will be de-asserted
again to start a new line. See Figure 11.
Figure 11. Default 1/4-Rate Line Timing for 1100 PCLKs
1/4-Rate Subsampling Mode Frame Timing
For the default 1/4-rate (1024x768)frame timing, the timing unit for the frame is derived from one line-time
unit, which is 1100 PCLKs. The frame timing starts when the VSYNC signal is de-asserted. The VSYNC
signal will be low for three line-time units. Eight line-time units from the start of the frame, DOUT [9:0]
will output five lines of dummy pixel data, followed by 240 lines of image data and another five lines of
dummy pixel data. Two lines after the last dummy pixel data, the VSYNC signal will be de-asserted again
to start a new frame. See Figure 12.
Figure 12. Default 1/4-Rate Frame Timing – Change Registers 0x14/0x15 to 0x0010 (H)
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3/14/2005