ICM320T Datasheet, PDF (25/30 Pages) List of Unclassifed Manufacturers – 3.2 Megapixel QXGA Digital Color CMOS Image Sensor

ICM320T
3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor
Preliminary Data Sheet V1.0
QXGA Full Resolution Mode Line Timing
For the default QXGA line timing, a line starts when the HSYNC signal is de-asserted. The HSYNC signal
will be low for 64 PCLK clock cycles. After 100 PCLK clock cycles, DOUT [9:0] will output ten cycles of
dummy pixel data followed by 2048 cycles of image data and ten cycles of dummy pixel data. Another 32
cycles later, the HSYNC signal will be de-asserted to start a new line. See Figure 9.
Figure 9. Default QXGA Line Timing for 2200 PCLKs
QXGA Full Resolution Mode Frame Timing
For the default QXGA frame timing, the timing unit for the frame is derived from one line-time unit, which
is 2200 PCLKs. Frame timing starts when the VSYNC signal is de-asserted. The VSYNC signal will be
low for three line-time units. Sixteen line-time units from the start of the frame, DOUT [9:0] will output ten
lines of dummy pixel data, followed by 1536 lines of image data and another ten lines of dummy pixel data.
248 lines after the image pixel data, the VSYNC signal will be de-asserted again to start a new frame. See
Figure 10.
Figure 10. Default QXGA Frame Timing – Change Registers 0x4/0x15 to 0x0010 (H)
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3/14/2005