ICM320T Datasheet, PDF (11/30 Pages) List of Unclassifed Manufacturers – 3.2 Megapixel QXGA Digital Color CMOS Image Sensor

ICM320T
3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor
Preliminary Data Sheet V1.0
Power Supply Noise Filtering
The ICM320T implements a power supply noise
filter for removal of power supply induced row
noise for improved low light image quality. The
row noise filter can be automatically enabled
when analog gain is applied, or manually
controlled. Register 0x3B[5] is used to select
manual or automatic mode. Manual control of
the filter is done through register 0x3B[6]. The
row noise filter can be programmed to a residual
image offset value. This value is set through
register 0x3C.
Fast Global Reset
The ICM320T implements a fast global reset
feature in support of low cost mechanical
shutters. With fast global reset, the ICM320T
image sensor array can be reset in 1.5ms @ 5fps
(PCLK=24 MHz). An example fast global reset
image capture sequence is described in Figure 6.
Figure 6. Fast Global Reset
Output Data Format
During normal operation, the output format is
10-bit raw data on the DOUT[9:0] data pins. In
addition to the data pins, the chip also outputs
VSYNC, HSYNC, and PCLK. The length and
polarity of the VSYNC and HSYNC signals can
be adjusted through registers 0x01[2:1] for
polarity; 0x18 and 0x19 for HSYNC length;
0x1A and 0x1B for VSYNC length . The line
and frame timing can be adjusted through
registers 0x0C-0x0F.
Pixel Clock
The pixel clock, PCLK, is a multiple of the
external clock. Although the output data is 10
bits, the internal ADC is 11 bits to minimize
quantization noise. Therefore, the ADC clock is
running at twice the frequency of the PCLK.
When the clock frequency changes, the RSET
resistor on the RES_REF pin as well as the
initialization file may also need to be changed.
The value of the RSET resistor is inversely
proportional to the ADC clock frequency. At 128
MHz ADC clock, the RSET is 12 kΩ; at 96 MHz
ADC clock, it is 16 Ω; at 48 MHz ADC clock, it
is 33 kΩ.
Power Down Mode
When the PWR_DOWN pin is de-asserted, the
chip goes into power down mode. In this state,
the internal clock is stopped. The PWR_DOWN
pin is not synchronized with the device clock.
The power down takes effect immediately. On
the assertion of the PWR_DOWN pin, the sensor
must wait at least 10 µs to leave the power down
mode to prevent the sensor from operating in an
unstable state.
Output Pin State Control
The state of the video output pins PCLK,
VSYNC, HSYNC, DOUT[9:0] is controlled by
the OEN pin or SIF register 0x4A[5:0]. Upon
power on reset or hard reset, the video pin output
state is determined by the configuration or the
OEN pin. If the OEN pin is asserted (active low),
the video outputs are enabled. If the OEN pin is
de-asserted, the video output pins are tri-stated.
SIF register 0x4A[5:0] can be used to override
the video pin output states independent of the
OEN pin configuration. The video output pins
are divided into three categories; CLK (PCLK),
SYNC (VSYNC, HSYNC) and DATA
(DOUT[9:0]). The output state for each output
pin category can be independently controlled.
Serial Control Interface (SIF)
The ICM320T sensor is fully compatible with
the I2C interface. Register programming is
through the SIF interface (SIF_SCL and
SIF_SDA pins). The default address for the 7-bit
SIF device is 0x20. The SIF_ID pin can
configure the last bit of the device address. The
ICM320T can operate in either SIF master mode
or in slave mode right after power up, depending
on the pull-up or pull-down of the SIF_MS pin.
When the SIF_MS pin is pulled down during
power up, the ICM320T’s SIF interface is
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3/14/2005