ICM320T Datasheet, PDF (24/30 Pages) List of Unclassifed Manufacturers – 3.2 Megapixel QXGA Digital Color CMOS Image Sensor

ICM320T
3.2 Megapixel QXGA Digital Color CMOS VGA Image Sensor
Preliminary Data Sheet V1.0
Sensor Timing
The following sections discuss the timing requirements and formats for the ICM320T image sensor. Note
that the timing requirements are related to the pixel clock and the format depends on the subsampling
mode.
Reset Timing
The reset timing reset signal RSTN must be asserted for more than two stable clock cycles. In addition, the
VDD voltage ramp must be above 90% of its specified value for more than two stable clock cycles as
shown in Figure 7.
Figure 7. Reset Timing
Pixel Output Timing
The pixel data and timing output signals are DOUT [9:0], PCLK, VSYNC, and HSYNC. Data should be
latched at the rising edge of the PCLK. The VSYNC and HSYNC signals are asserted and de-asserted at
the falling edge of the PCLK. See Figure 8.
Figure 8. Pixel Output Timing
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Page 24
3/14/2005