M13S64164A_09 Datasheet, PDF (7/48 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S64164A
AC Timing Parameter & Specifications-continued
Parameter
Half Clock Period
DQ-DQS output hold time
Data hold skew factor
ACTIVE to PRECHARGE command
Row Cycle Time
AUTO REFRESH Row Cycle Time
ACTIVE to READ,WRITE delay
PRECHARGE command period
ACTIVE to READ with AUTOPRECHARGE
command
Symbol
t_HP
t_QH
t_QHS
t_RAS
t_RC
t_RFC
t_RCD
t_RP
t_RAP
-5
min
t_CLmin or
t_CHmin
t_HP- t_QHS
-
40
60
70
15
15
15
ACTIVE bank A to ACTIVE bank B command
Write recovery time
Write data in to READ command delay
Col. Address to Col. Address delay
Average periodic refresh interval
Write preamble
Write postamble
DQS read preamble
DQS read postamble
Clock to DQS write preamble setup time
Load Mode Register / Extended Mode
register cycle time
t_RRD
t_WR
t_WTR
t_CCD
t_REFI
t_WPRE
t_WPST
t_RPRE
t_RPST
t_WPRES
t_MRD
10
15
2
1
-
0.25
0.4
0.9
0.4
0
2
Exit self refresh to READ command
Exit self refresh to non-READ command
Autoprecharge write recovery+Precharge
time
t_XSRD
t_XSNR
t_DAL
200
75
(t_WR/t_CK)
+
(t_RP/t_CK)
max
-
-
0.45
120K
-
-
-
-
120K
-
-
-
-
15.6
-
0.6
1.1
0.6
-
-
-
-
-6
min
t_CLmin or
t_CHmin
t_HP- t_QHS
-
42
60
72
18
18
max
-
-
0.5
120K
-
-
-
-
18
120K
12
-
18
-
2
-
1
-
-
15.6
0.25
-
0.4
0.6
0.9
1.1
0.4
0.6
0
-
1
-
200
-
75
-
(t_WR/t_CK)
+
(t_RP/t_CK)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t_CK
t_CK
us
t_CK
t_CK
t_CK
t_CK
ns
t_CK
t_CK
ns
t_CK
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.4
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