M13S64164A_09 Datasheet, PDF (15/48 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S64164A
Essential Functionality for DDR SDRAM
Burst Read Operation
Burst Read operation in DDR SDRAM is in the same manner as the current SDRAM such that the Burst read command is
issued by asserting CS and CAS low while holding RAS and WE high at the rising edge of the clock (CLK) after t_RCD from
the bank activation. The address inputs determine the starting address for the Burst, The Mode Register sets type of burst
(Sequential or interleave) and burst length (2, 4, 8). The first output data is available after the CAS Latency from the READ
command, and the consecutive data are presented on the falling and rising edge of Data Strobe (DQS) adopted by DDR SDRAM
until the burst length is completed.
<Burst Length = 4, CAS Latency = 3>
0
1
CLK
CL K
2
3
4
5
6
7
8
CO MMAND READ A
NOP
NO P
NOP
NO P
NOP
NOP
NOP
NO P
CAS L at ency=3
DQS
DQ' s
D out0 Do ut 1 Do ut2 D out3
Burst Write Operation
The Burst Write command is issued by having CS , CAS and WE low while holding RAS high at the rising edge of the
clock (CLK). The address inputs determine the starting column address. There is no write latency relative to DQS required for burst
write cycle. The first data of a burst write cycle must be applied on the DQ pins t_DS (Data-in setup time) prior to data strobe edge
enabled after t_DQSS from the rising edge of the clock (CLK) that the write command is issued. The remaining data inputs must be
supplied on each subsequent falling and rising edge of Data Strobe until the burst length is completed. When the burst has been
finished, any additional data supplied to the DQ pins will be ignored.
<Burst Length = 4>
0
1
CLK
CLK
2
3
4
COMMAND
NOP
DQS
DQ's
W RITE
NOP
NOP
tDQSS
tDSH
tDSS
tWPRES
NOP
tWPST
Din0 Din1 Din2 Din3
5
NOP
6
NOP
7
NOP
8
NOP
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.4
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