M13S64164A_09 Datasheet, PDF (1/48 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S64164A
DDR SDRAM
1M x 16 Bit x 4 Banks
Double Data Rate SDRAM
Features
z JEDEC Standard
z Internal pipelined double-data-rate architecture, two data access per clock cycle
z Bi-directional data strobe (DQS)
z On-chip DLL
z Differential clock inputs (CLK and CLK )
z DLL aligns DQ and DQS transition with CLK transition
z Quad bank operation
z CAS Latency : 2, 2.5, 3
z Burst Type : Sequential and Interleave
z Burst Length : 2, 4, 8
z All inputs except data & DM are sampled at the rising edge of the system clock(CLK)
z Data I/O transitions on both edges of data strobe (DQS)
z DQS is edge-aligned with data for reads; center-aligned with data for WRITE
z Data mask (DM) for write masking only
z V_DD = 2.3V ~ 2.7V, V_DDQ = 2.3V ~ 2.7V
z Auto & Self refresh
z 64ms refresh period, 4K cycle
z SSTL-2 I/O interface
z 66pin TSOPII and 60 ball BGA package
Ordering Information:
PRODUCT NO.
M13S64164A -5TG
M13S64164A -6TG
M13S64164A -5BG
M13S64164A -6BG
MAX FREQ
200MHz
166MHz
200MHz
166MHz
V_DD
2.5V
2.5V
PACKAGE COMMENTS
66TSOPII
Pb-free
BGA
Pb-free
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.4
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