M13S64164A_09 Datasheet, PDF (25/48 Pages) Elite Semiconductor Memory Technology Inc. – 1M x 16 Bit x 4 Banks Double Data Rate SDRAM

ESMT
M13S64164A
Power down
Power down is entered when CKE is registered low (no accesses can be in progress). If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is
referred to as active power-down. Entering power-down deactivates the input and output buffers, excluding CLK, CLK and CKE.
For maximum power savings, the user has the option of disabling the DLL prior to entering power-down. In that case, the DLL must
be enabled after exiting power-down, and 200 clock cycles must occur before a READ command can be issued. However,
power-down duration is limited by the refresh requirements of the device, so in most applications, the self-refresh mode is preferred
over the DLL disable power-down mode. In the power-down, CKE LOW and a stable clock signal must be maintained at the inputs
of the DDR SDRAM, and all other input signals are “Don’t Care”. The power-down state is synchronously exited when CKE is
registered HIGH (along with a NOP or DESELECT command). A valid executable command may be applied one clock cycle later.
CLK
CLK
tIS
CKE
COMMAND
VALID
NOP
No column
in
acess
pr ogr am
Enter
p ow er -dow n
mode
tIS
NOP
VALID
Exit power-down
mode
Elite Semiconductor Memory Technology Inc.
Publication Date : Jun. 2009
Revision : 1.4
25/48