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M12L128168A_09 Datasheet, PDF (5/45 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM
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ESMT
M12L128168A
AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V ，TA = 0 to 70 °C )
Parameter
Value
Unit
Input levels (Vih/Vil)
2.4/0.4
V
Input timing measurement reference level
1.4
V
Input rise and fall-time
tr/tf = 1/1
ns
Output timing measurement reference level
1.4
V
Output load condition
See Fig. 2
Output
870 Ω
3.3V
1200 Ω
VOH (DC) =2.4V , IOH = -2 mA
50pF
VOL (DC) =0.4V , IOL = 2 mA
Output
Z0 =50 Ω
Vtt = 1.4V
50 Ω
50pF
(Fig. 1) DC Output Load Circuit
(Fig. 2) AC Output Load Circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-5
Row active to row active delay
tRRD(min)
10
RAS to CAS delay
tRCD(min)
15
Row precharge time
tRP(min)
15
Row active time
tRAS(min)
38
tRAS(max)
@ Operating
tRC(min)
53
Row cycle time
@ Auto refresh tRFC(min)
55
Last data in to col. address delay
tCDL(min)
Last data in to row precharge
tRDL(min)
Last data in to burst stop
tBDL(min)
Refresh period (4,096 rows)
tBEF(max)
Version
-6
12
18
18
40
100
58
60
1
2
1
64
Unit
Note
-7
14
ns
1
20
ns
1
20
ns
1
42
ns
1
us
63
ns
1
70
ns
1,5
tCK
2
tCK
2
tCK
2
ms
6
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 2.3
5/45
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