M12L128168A_09 Datasheet, PDF (36/45 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L128168A
Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4
*Note : 1. DQM is needed to prevent bus contention
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 2.3
36/45