M12L128168A_09 Datasheet, PDF (4/45 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
M12L128168A
DC CHARACTERISTICS
Recommended operating condition unless otherwise noted，T_A = 0 to 70 °C
Parameter
Symbol
Test Condition
Operating Current
(One Bank Active)
Precharge Standby Current
in power-down mode
Precharge Standby Current
in non power-down mode
Active Standby Current
in power-down mode
I_CC1
I_CC2P
I_CC2PS
I_CC2N
I_CC2NS
I_CC3P
I_CC3PS
Burst Length = 1, t_RC ≥ t_RC(min), I_OL = 0 mA
CKE ≤ V_IL(max), tcc = t_CK(MIN)
CKE & CLK ≤ V_IL (max), t_CC = ∞
CKE ≥ V_IH(min), CS ≥ V_IH(min), t_CC = t_CK(MIN)
Input signals are changed one time during 2t_ck
CKE ≥ V_IH(min), CLK ≤ V_IL(max), tcc = ∞
input signals are stable
CKE ≤ V_IL(max), t_CC = t_CK(MIN)
CKE & CLK ≤ V_IL(max), t_CC = ∞
Active Standby Current
in non power-down mode
(One Bank Active)
Operating Current
(Burst Mode)
Refresh Current
Self Refresh Current
I_CC3N
I_CC3NS
I_CC4
I_CC5
I_CC6
CKE ^≥ V_IH(min), ^{CS ≥} V_IH(min), t_CC=15ns
Input signals are changed one time during 2clks
All other pins ^≥ V_DD-0.2V or ^≤ 0.2V
CKE ≥ V_IH(min), CLK ≤ V_IL(max), t_CC = ∞
input signals are stable
I_OL = 0 mA, Page Burst, 2 Banks activated
t_RC ≥ t_RC(min)
CKE ≤ 0.2V
Note : 1. Measured with outputs open.
2. Input signals are changed one time during 2 CLKS.
Version
-5 -6 -7
Unit Note
170 160 140 mA 1,2
2
mA
2
45
mA
25
6
mA
6
mA
55
35
mA
280 210 180 mA 1,2
280 210 180 mA
2
mA
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 2.3
4/45