M12L128168A_09 Datasheet, PDF (30/45 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
Read & Write Cycle at Same Bank @ Burst Length = 4
M12L128168A
*Note :
1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row
precharge. Last valid output will be Hi-Z (t_SHZ) after the clock.
3. Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst)
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 2.3
30/45