M12L128168A_09 Datasheet, PDF (44/45 Pages) Elite Semiconductor Memory Technology Inc. – 2M x 16 Bit x 4 Banks Synchronous DRAM

ESMT
Revision History
Revision
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
2.3
M12L128168A
Date
2002.10.31
2003.03.25
2003.09.02
2004.08.23
2005.03.17
2005.04.22
2005.06.07
2005.09.02
2006.09.08
2006.10.11
2006.10.24
2007.07.18
2009.02.23
2009.03.05
Description
Original
Modify die from 0.165mm to 0.15mm
Delete speed distribution -5 to prevent confusion of
customers
Correct typing error
1.Add Pb-free to ordering information
2.Modify P8 from bank precharge state to ldle state
Modify refresh spec
1.Modify tREF spec
2.Modify tRFC spec
Add revision history
Add -5T to ordering information
1.Modify AC parameter (tCH, tCL, tRP, tRAS, tRC)
2.Modify tSAC, tOH timing
Modify tRFC , tSHZ timing
Add BGA package
1.Rename A13,A12 to BA0,BA1
2.Modify the specification of tOH for -6 and -7
3.Modify the test condition of lIL and ICC3N
4.Modify the description about self refresh operation
Chang back to the specification of t_OH of the previous
version
Elite Semiconductor Memory Technology Inc.
Publication Date: Mar. 2009
Revision: 2.3
44/45