EN25D16 Datasheet, PDF (9/37 Pages) Eon Silicon Solution Inc. – 16 Megabit Serial Flash Memory

EN25D16
z In addition to the low power consumption feature, the Deep Power-down mode offers extra
software protection from inadvertent Write, Program and Erase instructions, as all instructions
are ignored except one particular instruction (the Release from Deep Power-down instruction).
TABLE 3. Protected Area Sizes Sector Organization
Status Register
Content
BP2 BP1 BP0
Bit Bit Bit
1
1
1
1
1
0
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
0
0
0
Memory Content
Protect Blocks
All
All
16 to 31
24 to 31
28 to 31
30 to 31
31
None
Addresses
000000h-1FFFFFh
000000h-1FFFFFh
100000h-1FFFFFh
180000h-1FFFFFh
1C0000h-1FFFFFh
1E0000h-1FFFFFh
1F0000h-1FFFFFh
None
Density(KB)
Portion
2048KB
2048KB
1024KB
512KB
256KB
128KB
64KB
None
All
All
Upper 1/2
Upper 1/4
Upper 1/8
Upper 1/16
Upper 1/32
None
Hold Function
The Hold (HOLD) signal is used to pause any serial communications with the device without reset-
ting the clocking sequence. However, taking this signal Low does not terminate any Write Status
Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (CS#) Low. The Hold
condition starts on the falling edge of the Hold (HOLD) signal, provided that this coincides with Serial
Clock (CLK) being Low (as shown in Figure 4.).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this coincides
with Serial Clock (CLK) being Low.
If the falling edge does not coincide with Serial Clock (CLK) being Low, the Hold condition starts af-
ter Serial Clock (CLK) next goes Low. Similarly, if the rising edge does not coincide with Serial Clock
(CLK) being Low, the Hold condition ends after Serial Clock (CLK) next goes Low. (This is shown in
Figure 4.).
During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DI)
and Serial Clock (CLK) are Don’t Care.
Normally, the device is kept selected, with Chip Select (CS#) driven Low, for the whole duration of
the Hold condition. This is to ensure that the state of the internal logic remains unchanged from the
moment of entering the Hold condition.
If Chip Select (CS#) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is necessary to
drive Hold (HOLD) High, and then to drive Chip Select (CS#) Low. This prevents the device from
going back to the Hold condition.
Figure 4. Hold Condition Waveform
This Data Sheet may be revised by subsequent versions
9
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2008/06/23