EN25D16 Datasheet, PDF (13/37 Pages) Eon Silicon Solution Inc. – 16 Megabit Serial Flash Memory

Table 6. Status Register Bit Locations
EN25D16
S7
S6
SRP
0
S5
S4
S3
S2
S1
S0
0
BP2
BP1
BP0
WEL
WIP
Status Register Protect
Reserved Bits
Block Protect Bits
Write Enable Latch
Write In Progress
Note : In OTP mode, SRP bit is served as OTP_LOCK bit.
The status and control bits of the Status Register are as follows:
WIP bit. The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to 0 no
such cycle is in progress.
WEL bit. The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable Latch is
reset and no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits. The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size
of the area to be software protected against Program and Erase instructions. These bits are written
with the Write Status Register (WRSR) instruction. When one or both of the Block Protect (BP2, BP1,
BP0) bits is set to 1, the relevant memory area (as defined in Table 3.) becomes protected against
Page Program (PP) Sector Erase (SE) and , Block Erase (BE), instructions. The Block Protect (BP2,
BP1, BP0) bits can be written provided that the Hardware Protected mode has not been set. The
Chip Erase (CE) instruction is executed if, and only if, both Block Protect (BP2, BP1, BP0) bits are 0.
Reserved bit. Status register bit locations 5 and 6 are reserved for future use. Current devices will
read 0 for these bit locations. It is recommended to mask out the reserved bit when testing the
Status Register. Doing this will ensure compatibility with future devices.
SRP bit / OTP_LOCK bit. The Status Register Protect (SRP) bit is operated in conjunction with the
Write Protect (WP#) signal. The Status Register Write Protect (SRP) bit and Write Protect (WP#)
signal allow the device to be put in the Hardware Protected mode (when the Status Register Protect
(SRP) bit is set to 1, and Write Protect (WP#) is driven Low). In this mode, the non-volatile bits of the
Status Register (SRP, BP2, BP1, BP0) become read-only bits and the Write Status Register (WRSR)
instruction is no longer accepted for execution.
In OTP mode, this bit is served as OTP_LOCK bit, user can read/program/erase OTP sector as
normal sector while OTP_LOCK value is equal 0, after OTP_LOCK is programmed with 1 by WRSR
command, the OTP sector is protected from program and erase operation. The OTP_LOCK bit can
only be programmed once.
Note : In OTP mode, the WRSR command will ignore any input data and program OTP_LOCK bit to
1, user must clear the protect bits before enter OTP mode and program the OTP code, then execute
WRSR command to lock the OTP sector before leaving OTP mode.
This Data Sheet may be revised by subsequent versions ₁₃ ©2004 Eon Silicon Solution, Inc., www.essi.com.tw
or modifications due to changes in technical specifications.
Rev. B, Issue Date: 2008/06/23