EN25D16 Datasheet, PDF (7/37 Pages) Eon Silicon Solution Inc. – 16 Megabit Serial Flash Memory

EN25D16
OPERATING FEATURES
SPI Modes
The EN25D16 is accessed through an SPI compatible bus consisting of four signals: Serial Clock
(CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus
operation Modes 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3, as shown in Figure 3, concerns the normal state of the CLK signal when the SPI bus
master is in standby and data is not being transferred to the Serial Flash. For Mode 0 the CLK signal
is normally low. For Mode 3 the CLK signal is normally high. In either case data input on the DI pin is
sampled on the rising edge of the CLK. Data output on the DO pin is clocked out on the falling edge
of CLK.
Figure 3. SPI Modes
Dual Output SPI
The EN25D16 supports Dual output operation when using the “ Dual Output Fast Read “ (3Bh)
instruction. This feature allows data to be transferred from the Serial Flash memory at twice the rate
possible with the standard SPI. This instruction is ideal for quickly downloading code from Flash to
RAM upon power-up (code-shadowing) or for application that cache code-segments to RAM for
execution. The Dual output feature simply allows the SPI input pin to also serve as an output during
this instruction. All other operations use the standard SPI interface with single output signal.
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one byte,
and a Page Program (PP) sequence, which consists of four bytes plus data. This is followed by the
internal Program cycle (of duration t_PP).
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be pro-
grammed at a time (changing bits from 1 to 0), provided that they lie in consecutive addresses on
the same page of memory.
Sector Erase, Block Erase and Chip Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be applied,
the bytes of memory need to have been erased to all 1s (FFh). This can be achieved a sector at a
time, using the Sector Erase (SE) instruction, a block at a time using the Block Erase (BE)
instruction or throughout the entire memory, using the Chip Erase (CE) instruction. This starts an
internal Erase cycle (of duration t_SE t_BE or t_CE). The Erase instruction must be preceded by a Write
Enable (WREN) instruction.
Polling During a Write, Program or Erase Cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase (SE, BE
or CE ) can be achieved by not waiting for the worst case delay (t_W, t_PP, t_SE, t_BE or t_CE). The Write In
Progress (WIP) bit is provided in the Status Register so that the application program can monitor its
value, polling it to establish when the previous Write cycle, Program cycle or Erase cycle is complete.
This Data Sheet may be revised by subsequent versions
7
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. B, Issue Date: 2008/06/23