EN25D16 Datasheet, PDF(10/37 Page) Eon Silicon Solution Inc.

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EN25D16 Datasheet, PDF (10/37 Pages) Eon Silicon Solution Inc. – 16 Megabit Serial Flash Memory

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EN25D16

INSTRUCTIONS

All instructions, addresses and data are shifted in and out of the device, most significant bit first.

Serial Data Input (DI) is sampled on the first rising edge of Serial Clock (CLK) after Chip Select (CS#)

is driven Low. Then, the one-byte instruction code must be shifted in to the device, most significant

bit first, on Serial Data Input (DI), each bit being latched on the rising edges of Serial Clock (CLK).

The instruction set is listed in Table 4. Every instruction sequence starts with a one-byte instruction

code. Depending on the instruction, this might be followed by address bytes, or by data bytes, or by

both or none. Chip Select (CS#) must be driven High after the last bit of the instruction sequence

has been shifted in. In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed

(Fast_Read), Read Status Register (RDSR) or Release from Deep Power-down, and Read Device

ID (RDI) instruction, the shifted-in instruction sequence is followed by a data-out sequence. Chip

Select (CS#) can be driven High after any bit of the data-out sequence is being shifted out.

In the case of a Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase (CE), Write

Status Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)

instruction, Chip Select (CS#) must be driven High exactly at a byte boundary, otherwise the

instruction is rejected, and is not executed. That is, Chip Select (CS#) must driven High when the

number of clock pulses after Chip Select (CS#) being driven Low is an exact multiple of eight. For

Page Program, if at any time the input byte is not a full byte, nothing will happen and WEL will not be

reset.

In the case of multi-byte commands of Page Program (PP), and Release from Deep Power

Down (RES ) minimum number of bytes specified has to be given, without which, the

command will be ignored.

In the case of Page Program, if the number of byte after the command is less than 4 (at least

1 data byte), it will be ignored too. In the case of SE and BE, exact 24-bit address is a must,

any less or more will cause the command to be ignored.

All attempts to access the memory array during a Write Status Register cycle, Program cycle or

Erase cycle are ignored, and the internal Write Status Register cycle, Program cycle or Erase cycle

continues unaffected.

Table 4. Instruction Set

Instruction Name Byte 1

Code

Write Enable

06h

Write Disable / Exit

OTP mode

04h

Read Status

05h

Write Status

01h

Read Data

03h

Fast Read

0Bh

Byte 2

Byte 3

(S7-S0)(1)

S7-S0

A23-A16

A15-A8

Dual Output Fast

Read

Page Program

Sector Erase

Block Erase

Chip Erase

Deep Power-down

3Bh

A23-A16

02h

A23-A16

20h

A23-A16

D8h/ 52h A23-A16

C7h/ 60h

B9h

A15-A8

Byte 4 Byte 5

A7-A0

(D7-D0)

dummy

A7-A0 dummy

A7-A0

D7-D0

Byte 6

n-Bytes

continuous(2)

(Next byte)

(D7-D0)

DI =

(D6, D4, D2, D0)

DO =

(D7, D5, D3, D1)

Next byte

continuous

(Next Byte)

continuous

(one byte

per 4 clocks,

continuous)

continuous

or modifications due to changes in technical specifications.

Rev. B, Issue Date: 2008/06/23

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