EN29LV040A_11 Datasheet, PDF (8/33 Pages) Eon Silicon Solution Inc. – 4 Megabit (512K x 8-bit ) Uniform Sector, CMOS 3.0 Volt-only Flash Memory

EN29LV040A
erase pulses and verifies the programmed /erased cells’ margin. The host system can detect
completion of a program or erase operation by reading the DQ[7] (Data# Polling) and DQ[6] (Toggle)
status bits.
The ‘Command Definitions’ section of this document provides details on the specific device commands
implemented in the EN29LV040A.
Sector Protection/Unprotection
The hardware sector protection feature disables both program and erase operations in any sector. The
hardware sector unprotection feature re-enables both program and erase operations in previously protected
sectors.
Sector protection/unprotection is intended only for programming equipment. This method requires V_ID
be applied to both OE# and A9 pin and non-standard microprocessor timings are used. This method is
described in a separate document called EN29LV040A Supplement, which can be obtained by contacting
a representative of Eon Silicon Solution, Inc.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy consumption. The device automatically
enables this mode when addresses remain stable for t_acc + 30ns. The automatic sleep mode is
independent of the CE#, WE# and OE# control signals. Standard address access timings provide new
data when addresses are changed. While in sleep mode, output is latched and always available to the
system. ICC₄ in the DC Characteristics table represents the automatic sleep more current specification.
Hardware Data Protection
The command sequence requirement of unlock cycles for programming or erasing provides data
protection against inadvertent writes as seen in the Command Definitions table. Additionally, the
following hardware data protection measures prevent accidental erasure or programming, which might
otherwise be caused by false system level signals during Vcc power up and power down transitions, or
from system noise.
Low V_CC Write Inhibit
When Vcc is less than V_LKO, the device does not accept any write cycles. This protects data during Vcc
power up and power down. The command register and all internal program/erase circuits are disabled,
and the device resets. Subsequent writes are ignored until Vcc is greater than V_LKO. The system must
provide the proper signals to the control pins to prevent unintentional writes when Vcc is greater than
V_LKO.
Write Pulse “Glitch” protection
Noise pulses of less than 5 ns (typical) on OE , CE or W E do not initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of OE = VIL, CE = VIH, or W E = VIH. To initiate a write
cycle, CE and W E must be a logical zero while OE is a logical one. If CE , W E , and OE are all
logical zero (not recommended usage), it will be considered a read.
Power-up Write Inhibit
During power-up, the device automatically resets to READ mode and locks out write cycles. Even with
CE = V_IL, W E = V_IL and OE = V_IH, the device will not accept commands on the rising edge of W E .
This Data Sheet may be revised by subsequent versions
8
or modifications due to changes in technical specifications.
© 2003 Eon Silicon Solution, Inc.,
Rev. E, Issue Date: 2011/10/27
www.eonssi.com