HB52D48GB-F Datasheet, PDF (6/23 Pages) Elpida Memory – 32 MB Unbuffered SDRAM Micro DIMM 4-Mword × 64-bit, 100 MHz Memory Bus, 1-Bank Module (4 pcs of 4 M × 16 components) PC100 SDRAM

HB52D48GB-F
Byte No. Function described
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Hex value Comments
20
SDRAM device attributes:
0 0 0 0 0 0 0 1 01
0
W latency
21
SDRAM module attributes
0 0 0 0 0 0 0 0 00
Unbuffer
22
SDRAM device attributes:
0 0 0 0 1 1 1 0 0E
General
V_CC ± 10%
23
SDRAM cycle time
1 0 1 0 0 0 0 0 A0
(2nd highest CE latency)
(-A6F/A6FL) 10 ns
CL = 2
(-B6F/B6FL) 15 ns
1 1 1 1 0 0 0 0 F0
24
SDRAM access from Clock 0 1 1 0 0 0 0 0 60
(2nd highest CE latency)
(-A6F/A6FL) 6 ns
(-B6F/B6FL) 8 ns
1 0 0 0 0 0 0 0 80
25
SDRAM cycle time
0 0 0 0 0 0 0 0 00
(3rd highest CE latency)
Undefined
26
SDRAM access from Clock (3rd 0 0 0 0 0 0 0 0 00
highest CE latency)
Undefined
27
Minimum row precharge time 0 0 0 1 0 1 0 0 14
20 ns
28
Row active to row active min 0 0 0 1 0 1 0 0 14
29
RE to CE delay min
0 0 0 1 0 1 0 0 14
30
Minimum RE pulse width
0 0 1 1 0 0 1 0 32
20 ns
20 ns
50 ns
31
Density of each bank on
0 0 0 0 1 0 0 0 08
module
32M byte
32
Address and command signal 0 0 1 0 0 0 0 0 20
2 ns
input setup time
33
Address and command signal 0 0 0 1 0 0 0 0 10
1 ns
input hold time
34
Data signal input setup time 0 0 1 0 0 0 0 0 20
2 ns
35
Data signal input hold time 0 0 0 1 0 0 0 0 10
1 ns
36 to 61 Superset information
0 0 0 0 0 0 0 0 00
Future use
62
SPD data revision code
0 0 0 1 0 0 1 0 12
Rev. 1.2A
63
Checksum for bytes 0 to 62 0 0 0 0 0 1 0 0 04
4
(-A6F/A6FL)
(-B6F/B6FL)
0 1 1 1 0 1 0 0 74
116
64
Manufacturer’s JEDEC ID code 0 0 0 0 0 1 1 1 07
HITACHI
65 to 71 Manufacturer’s JEDEC ID code 0 0 0 0 0 0 0 0 00
72
Manufacturing location
× × × × × × × × ××
*³ (ASCII-8bit
code)
Data Sheet E0011H10
6