HB52D48GB-F Datasheet, PDF (17/23 Pages) Elpida Memory – 32 MB Unbuffered SDRAM Micro DIMM 4-Mword × 64-bit, 100 MHz Memory Bus, 1-Bank Module (4 pcs of 4 M × 16 components) PC100 SDRAM

HB52D48GB-F
AC Characteristics (Ta = 0 to 65˚C, V_CC = 3.3 V ± 0.3 V, V_SS = 0 V)
HB52D48GB
-A6F/A6FL
-B6F/B6FL
Parameter
PC100
Symbol Symbol Min
Max Min
Max Unit
System clock cycle time
(CE latency = 2)
(CE latency = 3)
t _CK
Tclk
10
—
15
—
ns
t _CK
Tclk
10
—
10
—
ns
CK high pulse width
t _CKH
Tch
3
—
3
—
ns
CK low pulse width
t _CKL
Tcl
3
—
3
—
ns
Access time from CK
(CE latency = 2)
(CE latency = 3)
t _AC
Tac
—
6
—
8
ns
t _AC
Tac
—
6
—
6
ns
Data-out hold time
t _OH
Toh
3
—
3
—
ns
CK to Data-out low impedance t_LZ
2
—
2
—
ns
CK to Data-out high impedance t_HZ
—
6
—
6
ns
Data-in setup time
t_AS, t_CS, Tsi
2
t_DS, t_CES
—
2
—
ns
CKE setup time for power down t_CESP
exit
Tpde 2
—
2
—
ns
Data-in hold time
Ref/Active to Ref/Active
command period
t_AH, t_CH, Thi
1
t_DH, t_CEH
—
1
—
ns
t _RC
Trc
70
—
70
—
ns
Active to Precharge command t_RAS
period
Tras 50
120000 50
120000 ns
Active command to column
t _RCD
Trcd 20
—
20
—
ns
command (same bank)
Precharge to active command t_RP
Trp
20
—
20
—
ns
period
Write recovery or data-in to
t _DPL
Tdpl 10
—
10
—
ns
precharge lead time
Active (a) to Active (b)
command period
t _RRD
Trrd
20
—
20
—
ns
Transition time (rise and fall) t_T
Refresh period
t _REF
1
5
1
5
ns
—
64
—
64
ms
Notes
1
1
1
1, 2
1, 2
1, 2, 3
1, 4
1, 5, 6
1
1, 5
1
1
1
1
1
1
Data Sheet E0011H10
17