HB52D48GB-F Datasheet, PDF (15/23 Pages) Elpida Memory – 32 MB Unbuffered SDRAM Micro DIMM 4-Mword × 64-bit, 100 MHz Memory Bus, 1-Bank Module (4 pcs of 4 M × 16 components) PC100 SDRAM

HB52D48GB-F
DC Characteristics (Ta = 0 to 65°C, V_CC = 3.3 V ± 0.3 V, V_SS = 0 V)
HB52D48GB
-A6F/B6F/A6FL/B6FL
Parameter
Symbol Min
Max
Unit Test conditions
Notes
Operating current
I _CC1
—
Standby current in power down I_CC2P
—
Standby current in power down I_CC2PS —
(input signal stable)
Standby current in non power I_CC2N
—
down
Active standby current in power I_CC3P
—
down
Active standby current in non I_CC3N
—
power down
Burst operating current
Refresh current
Self refresh current
I _CC4
—
I _CC5
—
I _CC6
—
Self refresh current
(L-version)
I _CC6
—
260
mA Burst length = 1
1, 2, 3
t_RC = min
6
mA
CKE0 = V_IL, t_CK = 12 ns 6
4
mA
CKE0 = V_IL, t_CK = ∞ 7
40
mA
CKE0, S = V_IH,
4
t_CK = 12 ns
16
mA
CKE0, S = V_IH,
1, 2, 6
t_CK = 12 ns
72
mA
CKE0, S = V_IH,
1, 2, 4
t_CK = 12 ns
260
mA
t_CK = 12 ns, BL = 4 1, 2, 5
440
mA
t_RC = min
3
4
mA
V_IH ≥ V_CC – 0.2 V
8
V_IL ≤ 0.2 V
2.2
mA
Input leakage current
Output leakage current
I _LI
–10
10
I _LO
–10
10
µA
0 ≤ Vin ≤ V_CC
µA
0 ≤ Vout ≤ V_CC
DQ = disable
Output high voltage
V_OH
2.4
—
V
I_OH = –4 mA
Output low voltage
V_OL
—
0.4
V
I_OL = 4 mA
Notes: 1. I_CC depends on output load condition when the device is selected. I_CC (max) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK0/CK1 operating current.
7. After power down mode, no CK0/CK1 operating current.
8. After self refresh mode set, self refresh current.
Data Sheet E0011H10
15