HB52D48GB-F Datasheet, PDF (19/23 Pages) Elpida Memory – 32 MB Unbuffered SDRAM Micro DIMM 4-Mword × 64-bit, 100 MHz Memory Bus, 1-Bank Module (4 pcs of 4 M × 16 components) PC100 SDRAM

HB52D48GB-F
Relationship Between Frequency and Minimum Latency
Parameter
Frequency (MHz)
t_CK (ns)
Active command to column command
(same bank)
Active command to active command
(same bank)
Active command to precharge command
(same bank)
Precharge command to active command
(same bank)
Write recovery or data-in to precharge
command (same bank)
Active command to active command
(different bank)
Self refresh exit time
Last data in to active command
(Auto precharge, same bank)
Self refresh exit to command input
Symbol
l_RCD
l_RC
l_RAS
l_RP
l_DPL
l_RRD
l_SREX
l_APW
l_SEC
Precharge command to high impedance
(CE latency = 2)
l_HZP
(CE latency = 3)
l_HZP
Last data out to active command
l_APR
(auto precharge) (same bank)
Last data out to precharge (early precharge)
(CE latency = 2)
l_EP
(CE latency = 3)
l_EP
Column command to column command
l_CCD
Write command to data in latency
l_WCD
DQMB to data in
l_DID
DQMB to data out
l_DOD
CKE to CK disable
l_CLE
Register set to active command
l_RSA
PC100
Symbol
Tdpl
Tsrx
Tdal
Troh
Troh
Tccd
Tdwd
Tdqm
Tdqz
Tcke
Tmrd
HB52D48GB
-A6F/A6FL/B6F/B6FL
100
10
Notes
2
1
7
= [l_RAS+ l_RP]
1
5
1
2
1
1
1
2
1
1
2
4
= [l_DPL + l_RP]
7
= [l_RC]
3
2
3
1
–1
–2
1
0
0
2
1
1
Data Sheet E0011H10
19