HB52D48GB-F Datasheet, PDF (18/23 Pages) Elpida Memory – 32 MB Unbuffered SDRAM Micro DIMM 4-Mword × 64-bit, 100 MHz Memory Bus, 1-Bank Module (4 pcs of 4 M × 16 components) PC100 SDRAM

HB52D48GB-F
Notes: 1. AC measurement assumes t_T = 1 ns. Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is CL = 50 pF.
3. t_LZ (min) defines the time at which the outputs achieves the low impedance state.
4. t_HZ (max) defines the time at which the outputs achieves the high impedance state.
5. t_CES define CKE setup time to CK rising edge except power down exit command.
6. t_AS/t_AH: Address, t_CS/t_CH: S, RE, CE, W, DQMB
t_DS/t_DH: Data-in, t_CES/t_CEH: CKE
Test Conditions
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
input
2.4 V
2.0 V
0.4 V ^{0.8 V}
t_T
t_T
I/O
CL
Data Sheet E0011H10
18