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| HB52RF649E1U-75B Datasheet, PDF (4/20 Pages) Elpida Memory – 512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 133 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC133 SDRAM | |||
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HB52RF649E1U-75B
Pin No.
36
37
38
39
40
41
42
Pin name
A6
A8
A10 (AP)
BA1
VCC
VCC
CK0
Pin No.
78
79
80
81
82
83
84
Pin name
VSS
CK2
NC
WP
SDA
SCL
VCC
Pin No.
120
121
122
123
124
125
126
Pin name
A7
A9
BA0
A11
VCC
CK1
A12
Pin No.
162
163
164
165
166
167
168
Pin name
VSS
CK3
NC
SA0
SA1
SA2
VCC
Pin Description
Pin name
Function
A0 to A12
Address input
 Row address A0 to A12
 Column address A0 to A9, A11
BA0/BA1
Bank select address
DQ0 to DQ63
Data input/output
CB0 to CB7
Check bit (Data input/output)
S0, S2
Chip select input
RE
Row enable (RAS) input
CE
Column enable (CAS) input
W
Write enable input
DQMB0 to DQMB7
Byte data mask
CK0 to CK3
Clock input
CKE0
Clock enable input
WP
Write protect for serial PD
REGE*1
Register enable
SDA
Data input/output for serial PD
SCL
Clock input for serial PD
SA0 to SA2
Serial address input
VCC
Primary positive power supply
VSS
Ground
NC
No connection
Note: 1. REGE is the Register Enable pin which permits the DIMM to operate in âbufferedâ mode and
âregisteredâ mode. To conform to this specification, mother boards must pull this pin to high state
(âregisterdâ mode).
Preliminary Data Sheet E0023H10
4
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