HB52RF649E1U-75B Datasheet, PDF (16/20 Pages) Elpida Memory – 512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 133 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC133 SDRAM

HB52RF649E1U-75B
AC Characteristics (Ta = 0 to 55°C, V_CC = 3.3 V ± 0.3 V, V_SS = 0 V) (cont)
HB52RF649E1U-75B
PC133
PC100
CE latency = 4 CE latency = 3
Parameter
PC100
Symbol Symbol Min
Max Min
Max Unit Notes
Command setup time
t _CS
Command hold time
t _CH
Ref/Active to Ref/Active command t_RC
period
Tsi
1.9
—
Thi
1.5
—
Trc
67.5 —
2.6
—
1.6
—
70
—
ns 1
ns 1, 5
ns 1
Active to precharge command period t_RAS
Active command to column
t _RCD
command (same bank)
Tras 45
Trcd 20
120000 50
—
20
120000 ns 1
—
ns 1
Precharge to active command period t_RP
Trp
20
—
20
—
ns 1
Write recovery or data-in to
precharge lead time
t _DPL
Tdpl 7.5
—
10
—
ns 1
Active (a) to Active (b) command
t _RRD
Trrd 15
—
20
—
ns 1
period
Transition time (rise to fall)
t_T
1
5
1
5
ns
Refresh period
t _REF
—
64
—
64
ms
Notes: 1. AC measurement assumes t_T = 1 ns. Reference level for timing of input signals is 1.5 V.
2. Access time is measured at 1.5 V. Load condition is C_L = 50 pF.
3. t_LZ (max) defines the time at which the outputs achieves the low impedance state.
4. t_HZ (max) defines the time at which the outputs achieves the high impedance state.
5. t_CES defines CKE setup time to CK rising edge except power down exit command.
Test Conditions
• Input and output timing reference levels: 1.5 V
• Input waveform and output load: See following figures
input
2.4 V
2.0 V
0.4 V ^{0.8 V}
t_T
t_T
DQ
CL
Preliminary Data Sheet E0023H10
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