HB52RF649E1U-75B Datasheet, PDF (17/20 Pages) Elpida Memory – 512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 133 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC133 SDRAM

HB52RF649E1U-75B
Relationship Between Frequency and Minimum Latency
HB52RF649E1U-75B
Parameter
133
100
Frequency (MHz)
CE latency CE latency
=4
=3
t_CK (ns)
PC100
Symbol Symbol 7.5
10
Active command to column command (same bank) I_RCD
3
2
Active command to active command (same bank) I_RC
9
7
Notes
1
= [I_RAS + I_RP]
1
Active command to precharge command (same bank) I_RAS
6
5
1
Precharge command to active command (same bank) I_RP
3
2
1
Write recovery or data-in to precharge command
I _DPL
Tdpl 1
1
1
(same bank)
Active command to active command (different bank) I_RRD
2
2
1
Self refresh exit time
I _SREX
Tsrx 2
2
2
Last data in to active command
(Auto precharge, same bank)
I _APW
Tdal 4
3
= [I_DPL + I_RP]
Self refresh exit to command input
I _SEC
9
7
= [I_RC]
3
Precharge command to high impedance
Last data out to active command
(auto precharge) (same bank)
I _HZP
Troh 4
3
I _APR
0
0
Last data out to precharge (early precharge)
I _EP
–3
–2
Column command to column command
I _CCD
Tccd 1
1
Write command to data in latency
I _WCD
Tdwd 1
1
DQMB to data in
I _DID
Tdqm 1
1
DQMB to data out
I _DOD
Tdqz 3
3
CKE to CK disable
I _CLE
Tcke 2
2
Register set to active command
I _RSA
Tmrd 1
1
S to command disable
I _CDD
0
0
Power down exit to command input
I _PEC
1
1
Notes: 1. I_RCD to I_RRD are recommended value.
2. Be valid [DSEL] or [NOP] at next command of self refresh exit.
3. Except [DSEL] and [NOP]
Preliminary Data Sheet E0023H10
17