HB52RF649E1U-75B Datasheet, PDF (14/20 Pages) Elpida Memory – 512 MB Registered SDRAM DIMM 64-Mword × 72-bit, 133 MHz Memory Bus, 1-Bank Module (18 pcs of 64 M × 4 Components) PC133 SDRAM

HB52RF649E1U-75B
DC Characteristics (Ta = 0 to 55°C, V_CC = 3.3 V ± 0.3 V, V_SS = 0 V)
HB52RF649E1U-75B
PC133
PC100
CE latency = 4 CE latnecy = 3
Parameter
Symbol Min Max Min Max Unit Test conditions
Notes
Operating current
I _CC1
—
Standby current in power I_CC2P
—
down
2675 —
749 —
2675
749
mA Burst length = 1
t_RC = min
1, 2, 3
mA CKE = V_IL, t_CK = 12 ns 6
Standby current in power I_CC2PS —
down
(input signal stable)
731 —
731
mA CKE = V_IL, t_CK = ∞
7
Standby current in non
power down
I _CC2N
—
Active standby current in I_CC3P —
power down
1055 —
767 —
1055
767
mA CKE, S = V_IH,
4
t_CK = 12 ns
mA CKE = V_IL, t_CK = 12 ns 1, 2, 6
Active standby current in I_CC3N —
non power down
1235 —
1235
mA CKE, S = V_IH,
t_CK = 12 ns
Burst operating current
I _CC4
—
3035 —
2405 mA t_CK = min, BL = 4
Refresh current
I _CC5
—
4655 —
4655 mA t_RC = min
Self refresh current
I _CC6
—
749 —
749
mA V_IH ≥ V_CC – 0.2 V
V_IL ≤ 0.2 V
Input leakage current
I _LI
–10 10
–10 10
µA 0 ≤ Vin ≤ V_CC
Output leakage current
I _LO
–10 10
–10 10
µA 0 ≤ Vout ≤ V_CC
DQ = disable
1, 2, 4
1, 2, 5
3
8
Output high voltage
V_OH
2.4
—
2.4
—
V I_OH = –4 mA
Output low voltage
V_OL
—
0.4
—
0.4
V I_OL = 4 mA
Notes: 1. I_CC depends on output load condition when the device is selected. I_CC (max) is specified at the
output open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CK operating current.
7. After power down mode, no CK operating current.
8. After self refresh mode set, self refresh current.
Preliminary Data Sheet E0023H10
14