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| E1922E20 Datasheet, PDF (4/29 Pages) Elpida Memory – 4G bits DDR3L SDRAM | |||
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EDJ4204EFBG, EDJ4208EFBG, EDJ4216EFBG
Pin Configurations (Ã 16 configuration)
/xxx indicates active low signal.
96-ball FBGA
1
2
3
7
8
9
A
VDDQ DQU5 DQU7
B
VSSQ VDD VSS
C
VDDQ DQU3 DQU1
D
VSSQ VDDQ DMU
E
VSS VSSQ DQL0
F
VDDQ DQL2 DQSL
G
VSSQ DQL6 /DQSL
H
VREFDQ VDDQ DQL4
J
NC VSS /RAS
K
ODT VDD /CAS
L
NC /CS /WE
M
VSS BA0 BA2
N
VDD A3 A0
P
VSS A5 A2
R
VDD A7 A9
T
VSS /RESET A13
DQU4 VDDQ VSS
/DQSU DQU6 VSSQ
DQSU DQU2 VDDQ
DQU0 VSSQ VDD
DML VSSQ VDDQ
DQL1 DQL3 VSSQ
VDD VSS VSSQ
DQL7 DQL5 VDDQ
CK VSS NC
/CK VDD CKE
A10(AP) ZQ NC
NC VREFCA VSS
A12(/BC) BA1 VDD
A1 A4 VSS
A11 A6 VDD
A14 A8 VSS
(Top view)
Pin name
Function
Pin name
Function
A0 to A14*2
Address inputs
A10(AP): Auto precharge
A12(/BC): Burst chop
/RESET*2
Active low asynchronous reset
BA0 to BA2*2
Bank select
VDD
Supply voltage for internal circuit
DQU0 to DQU7
DQL0 to DQL7
Data input/output
VSS
Ground for internal circuit
DQSU, /DQSU
DQSL, /DQSL
/CS*2
/RAS, /CAS, /WE*2
CKE*2
Differential data strobe
Chip select
Command input
Clock enable
VDDQ
VSSQ
VREFDQ
VREFCA
Supply voltage for DQ circuit
Ground for DQ circuit
Reference voltage for DQ
Reference voltage for CA
CK, /CK
DMU, DML
ODT*2
Differential clock input
Write data mask
ODT control
ZQ
NC*1
Reference pin for ZQ calibration
No connection
Notes: 1. Not internally connected with die.
2. Input only pins (address, command, CKE, ODT and /RESET) do not supply termination.
Data Sheet E1922E20 (Ver. 2.0)
4
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