E1922E20 Datasheet, PDF (16/29 Pages) Elpida Memory – 4G bits DDR3L SDRAM

EDJ4204EFBG, EDJ4208EFBG, EDJ4216EFBG
Table 11: IDD4R and IDDQ4R Measurement-Loop Pattern
CK,
Sub Cycle Com-
A11
A7 A3 A0
/CK
CKE -Loop number mand /CS /RAS /CAS /WE ODT BA*³ -Am A10 -A9 -A6 -A2 Data*²
0
RD 0
1
0
1
0
0 0 0 0 0 0 00000000
1
D
1
0
0
0
0
0 0 0 000⎯
2,3
0
4
/D, /D 1
1
1
1
0
0 0 0 000⎯
RD 0
1
0
1
0
0 0 0 0 F 0 00110011
5
D
1
0
0
0
0
0 0 0 0 F0 ⎯
6,7
/D, /D 1
1
1
1
0
0 0 0 0 F0 ⎯
Toggling Static H 1
8 to 15 Repeat Sub-Loop 0, but BA= 1
2
16 to 23 Repeat Sub-Loop 0, but BA= 2
3
24 to 31 Repeat Sub-Loop 0, but BA= 3
4
32 to 39 Repeat Sub-Loop 0, but BA= 4
5
40 to 47 Repeat Sub-Loop 0, but BA= 5
6
48 to 55 Repeat Sub-Loop 0, but BA= 6
7
56 to 63 Repeat Sub-Loop 0, but BA= 7
Notes: 1.
2.
3.
4.
DM must be driven low all the time. DQS, /DQS are used according to read commands, otherwise MID-LEVEL.
Burst sequence driven on each DQ signal by read command. Outside burst operation, DQ signals are MID-LEVEL.
BA: BA0 to BA2.
Am: m means Most Significant Bit (MSB) of Row address.
Data Sheet E1922E20 (Ver. 2.0)
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