E1922E20 Datasheet, PDF (11/29 Pages) Elpida Memory – 4G bits DDR3L SDRAM

EDJ4204EFBG, EDJ4208EFBG, EDJ4216EFBG
1.4.2 Basic IDD and IDDQ Measurement Conditions
Table 6: Basic IDD and IDDQ Measurement Conditions
Parameter
Operating one bank
active precharge
current
Operating one bank
active-read-precharge
current
Precharge standby
current
Precharge standby
ODT current
Symbol
IDD0
IDD1
IDD2N
IDD2NT
Description
CKE: H; External clock: on; tCK, nRC, nRAS, CL: see Table 5; BL: 8*¹; AL: 0; /CS: H
between ACT and PRE; Command, address, bank address inputs: partially toggling
according to Table 7; Data I/O: MID-LEVEL; DM: stable at 0;
Bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see Table 7);
Output buffer and RTT: enabled in MR*²; ODT signal: stable at 0; Pattern details: see
Table 7
CKE: H; External clock: On; tCK, nRC, nRAS, nRCD, CL: see Table 5; BL: 8*^1, *⁶; AL:
0; /CS: H between ACT, RD and PRE; Command, address, bank address inputs, data
I/O: partially toggling according to Table 8;
DM: stable at 0; Bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,...
(see Table 8); Output buffer and RTT: enabled in MR*²; ODT Signal: stable at 0;
Pattern details: see Table 8
CKE: H; External clock: on; tCK, CL: see Table 5 BL: 8*¹; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: partially toggling according to Table 9;
data I/O: MID-LEVEL; DM: stable at 0; bank activity: all banks closed; output buffer
and RTT: enabled in mode registers*²; ODT signal: stable at 0; pattern details: see
Table 9
CKE: H; External clock: on; tCK, CL: see Table 5; BL: 8*¹; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: partially toggling according to Table 10;
data I/O: MID-LEVEL; DM: stable at 0; bank activity: all banks closed; output buffer
and RTT: enabled in MR*²; ODT signal: toggling according to Table 10; pattern
details: see Table 10
Precharge standby
ODT IDDQ current
Precharge power-down
current slow exit
Precharge power-down
current fast exit
Precharge quiet
standby current
Active standby current
Active power-down
current
Operating burst read
current
IDDQ2NT
IDD2P0
IDD2P1
IDD2Q
IDD3N
IDD3P
IDD4R
Same definition like for IDD2NT, however measuring IDDQ current instead of IDD
current
CKE: L; External clock: on; tCK, CL: see Table 5; BL: 8*¹; AL: 0; /CS: stable at 1;
Command, address, bank address inputs: stable at 0; data I/O: MID-LEVEL; DM:
stable at 0; bank activity: all banks closed; output buffer and RTT: EMR*²; ODT
signal: stable at 0; precharge power down mode: slow exit*³
CKE: L; External clock: on; tCK, CL: see Table 6; BL: 8*¹; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: stable at 0; data I/O: MID-LEVEL;
DM:stable at 0; bank activity: all banks closed; output buffer and RTT: enabled in
MR*²; ODT signal: stable at 0; precharge power down mode: fast exit*³
CKE: H; External clock: On; tCK, CL: see Table 5; BL: 8*¹; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: stable at 0; data I/O: MID-LEVEL;
DM: stable at 0;bank activity: all banks closed; output buffer and RTT: enabled in
MR*²; ODT signal: stable at 0
CKE: H; External clock: on; tCK, CL: see Table 5; BL: 8*¹; AL: 0; /CS: stable at 1;
Command, address, bank address Inputs: partially toggling according to Table 9;
data I/O: MID-LEVEL; DM: stable at 0;
bank activity: all banks open; output buffer and RTT: enabled in MR*²;
ODT signal: stable at 0; pattern details: see Table 9
CKE: L; External clock: on; tCK, CL: see Table 5; BL: 8*¹; AL: 0; /CS: stable at 1;
Command, address, bank address inputs: stable at 0; data I/O: MID-LEVEL;
DM:stable at 0; bank activity: all banks open; output buffer and RTT:
enabled in MR*²; ODT signal: stable at 0
CKE: H; External clock: on; tCK, CL: see Table 5; BL: 8*^1, *⁶; AL: 0; /CS: H between
RD; Command, address, bank address Inputs: partially toggling according to
Table 11; data I/O: seamless read
data burst with different data between one burst and the next one according to
Table 11; DM: stable at 0;
bank activity: all banks open, RD commands cycling through banks: 0,0,1,1,2,2,...
(see Table 11); Output buffer and RTT: enabled in MR*²; ODT signal: stable at 0;
pattern details: see Table 11
Operating burst read
IDDQ current
IDDQ4R
Same definition like for IDD4R, however measuring IDDQ current instead of IDD
current
Data Sheet E1922E20 (Ver. 2.0)
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