GD25Q80 Datasheet, PDF (8/49 Pages) ELM Electronics – 3.3V Uniform Sector Dual and Quad Serial Flash

GD25Q80CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
5. DATA PROTECTION
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The GD25Q80C provides the following data protection methods:
♦ Write Enable (WREN) command: The WREN command is set the Write Enable Latch bit (WEL). The WEL
bit will return to reset by the following situation:
- Power-Up
- Write Disable (WRDI)
- Write Status Register (WRSR)
- Page Program (PP)
- Sector Erase (SE) / Block Erase (BE) / Chip Erase (CE)
♦ Software Protection Mode: The Block Protect (BP4, BP3, BP2, BP1 and BP0) bits define the section of the
memory array that can be read but not change.
♦ Hardware Protection Mode: WP# going low to protected the BP0~BP4 bits and SRP0~1 bits.
♦ Deep Power-Down Mode: In Deep Power-Down Mode, all commands are ignored except the Release from
Deep Power-Down Mode command.
Table1.0 GD25Q80C Protected area size (CMP=0)
Status Register Content
Memory Content
BP4 BP3 BP2 BP1 BP0
××000
00001
00010
00011
00100
01001
01010
01011
01100
0×101
××11×
10001
10010
10011
1010×
11001
11010
11011
1110×
Blocks
NONE
15
14 to 15
12 to 15
8 to 15
0
0 to 1
0 to 3
0 to 7
0 to 15
0 to 15
15
15
15
15
0
0
0
0
Addresses
NONE
0F0000H-0FFFFFH
0E0000H-0FFFFFH
0C0000H-0FFFFFH
080000H-0FFFFFH
000000H-00FFFFH
000000H-01FFFFH
000000H-03FFFFH
000000H-07FFFFH
000000H-0FFFFFH
000000H-0FFFFFH
0FF000H-0FFFFFH
0FE000H-0FFFFFH
0FC000H-0FFFFFH
0F8000H-0FFFFFH
000000H-000FFFH
000000H-001FFFH
000000H-003FFFH
000000H-007FFFH
Density
NONE
64KB
128KB
256KB
512KB
64KB
128KB
256KB
512KB
1MB
1MB
4KB
8KB
16KB
32KB
4KB
8KB
16KB
32KB
Portion
NONE
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
ALL
Top Block
Top Block
Top Block
Top Block
Bottom Block
Bottom Block
Bottom Block
Bottom Block
49 - 8
Rev.1.0