GD25Q80 Datasheet, PDF (17/49 Pages) ELM Electronics – 3.3V Uniform Sector Dual and Quad Serial Flash

GD25Q80CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
7.5. Write Enable for Volatile Status Register (50H)
http://www.elm-tech.com
The non-volatile Status Register bits can also be written to as volatile bits. This gives more flexibility to
change the system configuration and memory protection schemes quickly without waiting for the typical non-
volatile bit write cycles or affecting the endurance of the Status Register non-volatile bits. The Write Enable for
Volatile Status Register command must be issued prior to a Write Status Register command. The Write Enable
for Volatile Status Register command will not set the Write Enable Latch bit, it is only valid for the Write Status
Register command to change the volatile Status Register bit values.
Figure 6. Write Enable for Volatile Status Register Sequence Diagram
CS#
SCLK
01234567
Command(50H)
SI
SO
High-Z
7.6. Read Data Bytes (READ) (03H)
The Read Data Bytes (READ) command is followed by a 3-byte address (A23-A0), each bit being latched-in
during the rising edge of SCLK. Then the memory content, at that address, is shifted out on SO, each bit being
shifted out, at a Max frequency fR, during the falling edge of SCLK. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shifted
out. The whole memory can, therefore, be read with a single Read Data Bytes (READ) command. Any Read
Data Bytes (READ) command, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 7. Read Data Bytes Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10
28 29 30 31 32 33 34 35 36 37 38 39
Command
24-bit address
SI
03H
23 22 21
3210
SO
High-Z
MSB
Data Out1
Data Out2
76543210
MSB
49 - 17
Rev.1.0