GD25Q80 Datasheet, PDF (16/49 Pages) ELM Electronics – 3.3V Uniform Sector Dual and Quad Serial Flash

GD25Q80CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash
7.3. Read Status Register (RDSR) (05H or 35H)
http://www.elm-tech.com
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read
at any time, even while a Program, Erase or Write Status Register cycle is in progress. When one of these cycles
is in progress, it is recommended to check the Write In Progress (WIP) bit before sending a new command to
the device. It is also possible to read the Status Register continuously. For command code “05H”, the SO will
output Status Register bits S7~S0. The command code “35H”, the SO will output Status Register bits S15~S8.
Figure 4. Read Status Register Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Command
SI
05H or 35H
SO
High-Z
S7~S0 or S15~S8 out
S7~S0 or S15~S8 out
76543210765432107
MSB
MSB
7.4. Write Status Register (WRSR) (01H)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. Before it
can be accepted, a Write Enable (WREN) command must previously have been executed. After the Write Enable
(WREN) command has been decoded and executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) command has no effect on S15, S1 and S0 of the Status Register. CS# must
be driven high after the eighth or sixteen bit of the data byte has been latched in. If not, the Write Status Register
(WRSR) command is not executed. If CS# is driven high after eighth bit of the data byte, the CMP and QE bit
will be cleared to 0. As soon as CS# is driven high, the self-timed Write Status Register cycle (whose duration
is tW) is initiated. While the Write Status Register cycle is in progress, the Status Register may still be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed
Write Status Register cycle, and is 0 when it is completed. When the cycle is completed, the Write Enable Latch
(WEL) is reset.
The Write Status Register (WRSR) command allows the user to change the values of the Block Protect (BP4,
BP3, BP2, BP1 and BP0) bits, to define the size of the area that is to be treated as read-only, as defined in
Table1. The Write Status Register (WRSR) command also allows the user to set or reset the Status Register
Protect (SRP) bit in accordance with the Write Protect (WP#) signal. The Status Register Protect (SRP) bit
and Write Protect (WP#) signal allow the device to be put in the Hardware Protected Mode. The Write Status
Register (WRSR) command is not executed once the Hardware Protected Mode is entered.
Figure 5. Write Status Register Sequence Diagram
CS#
SCLK
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
Command
Status Register in
SI
01H
7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8
SO
MSB
High-Z
49 - 16
Rev.1.0