GD25Q80 Datasheet, PDF(32/49 Page) ELM Electronics – 3.3V Uniform Sector Dual and Quad Serial Flash

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GD25Q80 Datasheet, PDF (32/49 Pages) ELM Electronics – 3.3V Uniform Sector Dual and Quad Serial Flash

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GD25Q80CxIGx 3.3V Uniform Sector Dual and Quad Serial Flash

7.25. Continuous Read Mode Reset (CRMR) (FFH)

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The Dual/Quad I/O Fast Read operations, âContinuous Read Modeâ bits (M7-0) are implemented to further

reduce command overhead. By setting the (M7-0) to AXH, the next Dual/Quad I/O Fast Read operations do not

require the BBH/EBH/E7H command code.

Because the GD25Q80C has no hardware reset pin, so if Continuous Read Mode bits are set to âAXHâ, the

GD25Q80C will not recognize any standard SPI commands. So Continuous Read Mode Reset command will

release the Continuous Read Mode from the âAXHâ state and allow standard SPI command to be recognized.

The command sequence is show in Figure30.

Figure 30. Continuous Read Mode Reset Sequence Diagram

CS#

SCLK

Mode Bit Reset for Quad/Dual I/O

01234567

SI(IO0)

SO(IO1)

WP#(IO2)

HOLD#(IO3)

FFH

Don`t Care

7.26. Program/Erase Suspend (PES) (75H)

The Program/Erase Suspend command â75Hâ, allows the system to interrupt a page program or sector/block

erase operation and then read data from any other sector or block. The Write Status Register command (01H)

and Erase/Program Security Registers command (44H, 42H) and Erase commands (20H, 52H, D8H, C7H,

60H) and Page Program command (02H/32H) are not allowed during Program/Erase suspend. Program/Erase

Suspend is valid only during the page program or sector/block erase operation. A maximum of time of âtsusâ (See

AC Characteristics) is required to suspend the program/erase operation.

The Program/Erase Suspend command will be accepted by the device only if the SUS bit in the Status Register

equal to 0 and WIP bit equal to 1 while a Page Program or a Sector or Block Erase operation is on-going. If

the SUS bit equal to 1 or WIP bit equal to 0, the Suspend command will be ignored by the device. The WIP bit

will be cleared from 1 to 0 within âtsusâ and the SUS bit will be set from 0 to 1 immediately after Program/

Erase Suspend. A power-off during the suspend period will reset the device and release the suspend state. The

command sequence is show in Figure31.

Figure 31. Program/Erase Suspend Sequence Diagram

CS#

SCLK

01234567

Command

75H

High-Z

tSUS

Accept read command

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Rev.1.0

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