GD25D10 Datasheet, PDF (13/28 Pages) ELM Electronics – Uniform sector dual and quad serial flash

GD25D10BxIGx Uniform sector dual and quad serial flash
7.7. Dual Output Fast Read (3BH)
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The Dual Output Fast Read command is followed by 3-byte address (A23-A0) and a dummy byte, each bit
being latched in on the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle
from SI and SO. The command sequence is shown in followed Figure7. The first byte addressed can be at any
location. The address is automatically incremented to the next higher address after each byte of data is shifted
out.
Figure 7. Dual Output Fast Read Sequence Diagram
7.8. Page Program (PP) (02H)
The Page Program (PP) command is for programming the memory. A Write Enable (WREN) command must
previously have been executed to set the Write Enable Latch (WEL) bit before sending the Page Program
command.
The Page Program (PP) command is entered by driving CS# Low, followed by the command code, three
address bytes and at least one data byte on SI.
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes beyond the end
of the current page are programmed from the start address of the same page (from the address whose 8 least
significant bits (A7-A0) are all zero). CS# must be driven low for the entire duration of the sequence.
The Page Program command sequence: CS# goes low → sending Page Program command → 3-byte address
on SI → at least 1 byte data on SI→ CS# goes high. The command sequence is shown in Figure8.
If more than 256 bytes are sent to the device, previously latched data are discarded and the last 256 data bytes
are guaranteed to be programmed correctly within the same page. If less than 256 data bytes are sent to device,
they are correctly programmed at the requested addresses without having any effects on the other bytes of the
same page. CS# must be driven high after the eighth bit of the last data byte has been latched in; otherwise the
Page Program (PP) command is not executed.
As soon as CS# is driven high, the self-timed Page Program cycle (whose duration is tPP) is initiated. While the
Page Program cycle is in progress, the Status Register may be read to check the value of the Write in Progress
(WIP) bit. The Write in Progress (WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
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