GD25D10 Datasheet, PDF (10/28 Pages) ELM Electronics – Uniform sector dual and quad serial flash

GD25D10BxIGx Uniform sector dual and quad serial flash
7.1. Write Enable (WREN)(06H)
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The Write Enable (WREN) command is for setting the Write Enable Latch (WEL) bit to 1. The Write Enable
Latch (WEL) bit must be set prior to every Page Program (PP), Sector Erase (SE), Block Erase (BE), Chip Erase
(CE) and Write Status Register (WRSR) command.
The Write Enable (WREN) command sequence: CS# goes low → sending the Write Enable command → CS#
goes high.
Figure 1. Write Enable Sequence Diagram
CS#
SCLK
SI
SO
01234567
Command
06H
High-Z
7.2. Write Disable (WRDI) (04H)
The Write Disable command is for resetting the Write Enable Latch (WEL) bit to 0. The WEL bit is reset by
following condition: Power-up and upon completion of the Write Status Register, Page Program, Sector Erase,
Block Erase and Chip Erase commands.
The Write Disable command sequence: CS# goes low → Sending the Write Disable command → CS# goes
high.
Figure 2. Write Disable Sequence Diagram
CS#
SCLK
SI
SO
01234567
Command
04H
High-Z
7.3. Read Status Register (RDSR) (05H)
The Read Status Register (RDSR) command is for reading the Status Register. The Status Register may be read
at any time, even while a Program, Erase or Write Status Register cycle is in progress.
When one of these cycles is in progress, it is recommended to check the Write in Progress (WIP) bit before
sending a new command to the device. It is also possible to read the Status Register continuously. For command
code “05H”, the SO will output Status Register bits S7~S0.
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Rev.1.0