MA31753 Datasheet, PDF (9/30 Pages) Dynex Semiconductor – DMA Controller (DMAC) For An MA31750 System

5.1 MODE / LINK WORD
MA31753
Mode
A1M
A2M SEOT C
Next Instruction
D0
D15
Mode 000: Single word
001: Double word
010: Burst mode
011: not used (channel not started)
100: Area to Area, Memory to Memory
101: Area to Area, Memory to IO
110: Area to Area, IO to Memory
111: Area to Area, IO to IO
A1M
Area 1 Mode
For single, double and burst modes
00: Read from memory, incrementing address
01: Read from memory, decrementing address
10: Write to memory, incrementing address
11: Write to memory, decrementing address
Area to area mode
00: Area 1 address constant
01: Area 1 address incrementing
10: Area 1 address decrementing
11: Area 1 address constant
A2M
Area 2 Mode (only used in area to area mode)
00: Area 2 address constant
01: Area 2 address incrementing
10: Area 2 address decrementing
11: Area 2 address constant
SEOT 0:
1:
Signal ‘End of Transfer’ at end of current block only of C=0
Always signal ‘End of Transfer’ at end of current block.
C
read 0: Perform no chaining
read 1: Perform chaining using the value of “next Instruction” field as pointer
write 0: Perform no chaining even if defined by current DMA instruction
write 1: Perform chaining as defined by current instruction
Next These 6 bits give the number of the next instruction to be executed. If the number is 3C, 3D, 3E or 3F, then the DMA
Inst transfers will stop with the current block.
5.2 BLOCK LENGTH
Block Length
D0
D15
This readable and writable 16-bit word gives the number of words to be transferred for the current DMA block.
5.3 AREA 1 AND 2 BASE ADDRESSES
Base Address
D0
D15
These registers hold the addresses of the first word of memory or IO to be transferred (ie. when the channel is decrementing
the address, this register holds the highest address to be transferred.)
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