MA31753 Datasheet, PDF (11/30 Pages) Dynex Semiconductor – DMA Controller (DMAC) For An MA31750 System

MA31753
6.0 PIN DESCRIPTIONS
A[0:15]
I/O A[0] is the most significant bit of this logical address bus. This bus is an input during cycles not assigned to the
DMA and is driven during DMA cycles.
PB[0:3]
O Used in 1750B mode only, this bus provides DMA page bank information which addresses up to 8M of memory.
The bus is tri-stated during cycles not assigned to the DMA.
AS[0:3]
O This bus indicates the current address state of the DMA controller. It is tri-stated during cycles not assigned to the
DMA.
PS[0:3]
O This bus indicates the current process state of the DMA controller. It is tri-stated during cycles not assigned to the
DMA.
D[0:16]
I/O D[0] is the most significant bit of the data bus. During DMA cycles, data is input on read cycles and output on write
cycles. D[16] is the parity bit. Odd or even parity is set in the configuration word. Parity is not used during DMA
writes to memory.
CLK
I Input clock signal
RESETN
I This active low signal resets the DMA.
CSN
I When low, access to read and write the DMA internal registers is enabled.
AS
I/O AS high indicates the presence of a valid address on the address bus. This signal is an input on cycles not
assigned to the DMA.
DSN
I/O When low, data strobe indicates the presence of data on the data bus. This signal is an input on cycles not assigned
to the DMA.
MION
I/O If high, this signal indicates that the current cycle is accessing memory space. If low, the current cycle is
accessing IO space. Is an input during cycles not assigned to the DMA.
RDWN
I/O During DMA cycles, this signal goes high to indicate read cycles and low to indicate write cycles. It is an input
during non-DMA cycles.
OIN
O During DMA cycles, this signal goes high to indicate operand cycles and low to indicate instruction cycles. It is tri-
stated during non-DMA cycles.
RDN
O This active low read strobe is tri-stated on non-DMA cycles.
WRN
O This active low write strobe is tri-stated on non-DMA cycles.
RDYN
I/O This signal goes active low to indicate that the current bus cycles can be terminated. It is an output on cycles
addressing the DMA internal registers, input on cycles controlled by the DMA and is tri-stated during all other
cycles.
LOCKN
O This signal is driven low during the first bus cycle of a double word transfer. It should be used by the bus arbiter to
'lock' bus control to the DMA. It is tri-stated during cycles not assigned to the DMA.
REQN
O Always driven, this signal goes low to indicate that the DMA requests the bus.
GRANTN
I Sampled by the DMA on negative CLK edges, this signal goes low to indicate that the DMA has bus control.
DMAKN
O This output is driven active low by the DMA when it has bus control. It is tri-stated on cycles not assigned to the
DMA.
DONEN
O This signal is pulsed low for one CLK cycle when any of the four DMA channels reaches an 'end of transfer'
condition.
REQINN
I Sampled by the DMA on negative CLK edges, a low on this input indicates that a cascaded, lower priority DMA is
requesting the bus. This input should be tied high in a single DMA system.
GEINN
I This active low signal is used to qualify the GRANTN signal for cascaded DMA devices. This signal should be tied
low on the first DMA of the chain.
GEOUTN O This active low output indicates that a lower priority DMA will be granted the bus when the GRANTN signal is
asserted low from the arbiter. It is used to cascade DMA devices by connecting to the GEINN pin of the next DMA.
INTRN
O This active low interrupt request signal pulses low when an 'end of transfer' or an internal error condition are
detected.
PEN
I The DMA samples PEN on AS falling. If an error condition is sampled, the transfer on the DMA channel is stopped
and the CLE bit is set in the Channel Status Register.
DMAE
I An active high input to indicate that the DMA is enabled. If this input is low, internal requests are supressed, there is
no response to external requests and REQINN is gated out internally.
DPARN
I A low on this signal resets and disables checking of the parity bit (D[16])
DTON
I A low on this signal resets and disables the bus fault timeout circuitry.
MPROEN
I This input is sampled on AS falling when the DMA has bus control. If an active low is sampled, the transfer stops
on the channel concerned and the CAE (addressing error) bit is set in the channel status register. An interrupt may
be generated.
EXADEN
I This input is sampled on AS falling when the DMA has bus control. If an active low is sampled, the transfer stops
on the channel concerned and the CAE (addressing error) bit is set in the channel status register. An interrupt may
be generated.
DREQN[0:3] I Sampled by the DMA on negative CLK edges, a low on this bus initiates a DMA transfer providing the
corresponding channel is correctly set up and is not masked. When the pin is pulled high, the ongoing bus cycle
will terminate.
DACKN[0:3] O During a transfer, the DMA drives the relevant channel acknowledge low to indicate that the DMA is ready for the
data. The low to high transition at the end of the cycle is initiated by the condition DREQN high and RDYN low.
SEC/FIRSTN O A high indicates that the first word in a transfer is occuring. A low indicates that the second word in a double word
transfer is occuring.
AKRDN
O This active low strobe indicates that the DMA is driving the data bus.
AKWRN
O This active low strobe indicates that the DMA is inputting data from the data bus.
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