MA31753 Datasheet, PDF (7/30 Pages) Dynex Semiconductor – DMA Controller (DMAC) For An MA31750 System

MA31753
4.2 REMAINING WORD REGISTERS
Current Block Counter
D0
D15
Read access only. These 16-bit registers store the number of words left to be transferred for each area.
4.3 CURRENT ADDRESS REGISTERS
Current Address
D0
D15
Read access only. These 16-bit registers store the addresses of the current words to be transferred to / from the area
represented by the register.
4.4 CURRENT PB / PS / AS REGISTER
OIN
PB0
PB3 PS0
PS3 AS0
AS3
D0
D15
Read access only. These 16-bit registers store the current page bank, address and process state information for each area.
When the areas have been selected within the IO space, PB, PS and AS shall be zero.
4.5 STATUS REGISTERS
CA EOT CRQP
IPE BLE BIE CLE
Interval
D0
D15
CA
0: Channel not active
1: Channel active
This bit is automatically set to zero at an error or EOT condition.
EOT
0: Channel EOT not reached
1: Channel EOT reached.
CRQP
0: No channel DMA request pending.
1: Channel DMA request pending.
It is not possible to reset this bit as long as a DREQN line is asserted.
IPE
0: No internal parity error
1: Internal parity error when reading DMA register with parity.
BLE
0: No error
1: Block length error (odd block length in double word mode)
BIE
0: No error
1: Bus interface timeout error (caused either by not deasserting DREQN in handshake mode or by a bus timeout)
CLE
0: No error
1: CPU latched error (either MPROEN, EXADEN or PEN)
Interval The interval, in CLK cycles, between each DMA request generated during area to area transfers.
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