MA31753 Datasheet, PDF (4/30 Pages) Dynex Semiconductor – DMA Controller (DMAC) For An MA31750 System

MA31753
3.6.4 Area to Area Mode
In area to area mode, the transfers can be initiated either
by external requests or internally generated by the DMA
depending on the value in the interval timer (the software
generated requests controlleed by the interval timer can only
be used on channels 0 and 1). Each request makes the DMA
request bus control for 2 machine cycles. The transfers can
take place to and from IO and / or memory depending on how
the instruction programs the channel. The DMA de-asserts the
request during the second cycle unless the instruction has
programmed the channel to do “Continuous Internal Request”.
In this case, the request is only de-asserted on the last cycle of
the block. If extended bus cycles are needed, the RDYN
mechanism must be used as the handshaking does not work in
this mode.
3.6.5 Instruction Chaining
When the first request is received on a channel, it
accesses the DMA instruction number that is programmed in
the mode word. This instruction is read from internal DMA
RAM. This takes 16 CLK cycles (as there are 8 16-bit word in
the instruction). Bus control is not needed during these internal
RAM accesses. At the end of the 16 CLK cycles, the channel
has all the transfer information it needs and can begin to
transfer whenever it is granted bus control. Once the transfer
has completed, the channel checks that it is in chaining mode
and that the instruction is a chained instruction. If so, then as
the first instruction completes, the DMA can access the next
instruction (again taking 16 CLK cycles) and the transfers can
continue as bus control is granted.
3.6.6 Handshaking Mechanism
There is a handshaking mechanism available when using
single-word transfer mode. It works as follows:
For a memory read cycle:
1: The IO port issues a request.
2: The DMA requests and is granted bus control. The DMA
starts a memory read cycle. As well as the usual control
and strobes, the DMA also asserts the DACKN low for the
channel that it is responding to. The DACKN signal acts as
an IO port select.
3: Once valid data is available on the data bus ie. RDYN has
gone low, the DMA asserts AKWRN low. The IO port uses
AKWRN as a write strobe.
4: The IO port acknowledges the completed data read by de-
asserting DREQN.
5: When the DMA sees DREQN has gone high, it de-asserts
DACKN. At this time, the data is still valid and the IO port
may latch the data on AKWRN rising or any time in
between.
6: The DMA completes the cycle by de-asserting strobes etc.
7: The wait state generator finally de-asserts RDYN.
For a memory write cycle:
1: The IO port issues a request.
2: The DMA aquires bus control and starts a memory write
cycle, also asserting DACKN for the relevant channel.
3: The data bus is driven by the IO port. Valid data is
available when the IO port de-asserts DREQN. (DACKN is
still asserted so valid data must still be driven on the bus).
4: When the DMA senses DREQN high, it writes the valid
data from the IO port into memory.
5: The memory write is completed when RDYN goes low.
6: The DMA de-asserts DACKN and hence the IO port stops
driving the data bus.
If DREQN is de-asserted 2 or more CLK cycles before
AKRDN or AKWRN are asserted, then the handshaking
protocol does not apply and the cycle will simply use the RDYN
signal going low to terminate the cycle (both AKRDN and
AKWRN will rise as AS falls at the end of the cycle).
3.7 INTERRUPT GENERATION
The DMA shall generate an interrupt on the occurrance of
any of the following:
- A channel has reached an “End of Transfer” condition and
the EOT bit has been set in the channel status register.
- A channel has been stopped because
a) a bus timeout has occurred. (ie. either DREQN
(handshake mode) or RDYN is asserted for more than
256 CLK cycles)
b) an internal parity error was detected when reading a
DMA register with parity.
c) An odd block length was programmed in double word
mode.
The DMA will stop but will not generate an interrupt if
EXADEN, MPROEN or PEN are active at the end of an
external cycle.
If a parity error is detected whilst writing to the DMA
registers, the erroneous write will not let transfers commence.
The DMA generates interrupts by pulsing INTRN low. If more
than one error occurs simultaneously, INTRN is only pulsed
once. The interrupt can only be generated when the DMA is in
the ERROR mode. The only way to get out of this mode is to
reset all error flags.
3.8 CHANNEL MASKING AND STOPPING
Each channel can be masked individually by setting the
relevant bit in the DMA Mode / Status register. If the channel is
masked, only external requests are gated out - software
requests are still serviced.
Each channel can be stopped by de-activating the channel
by writing the Channel Mode register. This register can only be
written whilst in PEND_CHAIN mode or awaiting bus control.
Once the channel is de-activated, it returns to the IDLE mode.
3.9 PARITY CHECKING
Parity checks are done when DMA registers are being
written and when they are being accessed ie. when the
instructions are being read.
4/30