MA31753 Datasheet, PDF (8/30 Pages) Dynex Semiconductor – DMA Controller (DMAC) For An MA31750 System

MA31753
4.6 DMA MODE / STATUS 1
M3 M2 M1 M0 EOT3 EOT2 EOT1 EOT0 ERR A/B
BP DMAE Priority
D0
D15
Mn 0: Channel n not masked
1: Channel n masked
EOTn 0: Channel n “End of Transfer” not reached
1: Channel n “End of Transfer” reached
Read access only. Value can be changed by writing the channel status register.
ERR
0: No error detected
1: Error detected in one or more of the channels
Read access only. Value can be changed by writing the channel status register.
A / B 0: 1750A mode
1: 1750B mode
BP
0: Even bus parity used
1: Odd bus parity used
DMAE 0: DMA requests disabled
1: DMA requests enabled
Read access only
Pri
000: Channel priority 0, 1, 2, 3, C
001: Channel priority 1, 2, 3, 0, C
010: Channel priority 2, 3, 0, 1, C
011: Channel priority 3, 0, 1, 2, C
100: Channel priority C, 0, 1, 2, 3
101: Channel priority C, 1, 2, 3, 0
110: Channel priority C, 2, 3, 0, 1
111: Channel priority C, 3, 0, 1, 2
5.0 DMA INSTRUCTIONS
60 DMA instructions are present in the memory or IO space between A[7:15] = 0 and A[7:15] = 1DF. Each DMA instruction
comprises of 8 16-bit words. The base address for each instruction is 8*n where n is the instruction number. The instructions are
structured as below:
Word numbe r
0
1
2
3
4
5
6
7
Content
Mode/Link word
Block length
Area 1 base address
Area 1 PB, PS and AS
Area 2 base address
Area 2 PB, PS and AS
Transfer interval
Not used
Words 4, 5 and 6 are used only during area to area mode transfers. Word 6 can only be used for channels 0 and 1.
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